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Xiangfu Liu80421fc2011-10-12 12:24:06 +08001/*
2 * Jz4740 common routines
3 * Copyright (c) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#include <config.h>
22#include <common.h>
23#include <asm/io.h>
24#include <asm/jz4740.h>
25
26void enable_interrupts(void)
27{
28}
29
30int disable_interrupts(void)
31{
32 return 0;
33}
34
35/*
36 * PLL output clock = EXTAL * NF / (NR * NO)
37 * NF = FD + 2, NR = RD + 2
38 * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
39 */
40void pll_init(void)
41{
42 struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
43
44 register unsigned int cfcr, plcr1;
45 int n2FR[33] = {
46 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
47 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
48 9
49 };
50 int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
51 int nf, pllout2;
52
53 cfcr = CPM_CPCCR_CLKOEN |
54 CPM_CPCCR_PCS |
55 (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
56 (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
57 (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
58 (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
59 (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
60
61 pllout2 = (cfcr & CPM_CPCCR_PCS) ?
62 CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
63
64 /* Init USB Host clock, pllout2 must be n*48MHz */
65 writel(pllout2 / 48000000 - 1, &cpm->uhccdr);
66
67 nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
68 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
69 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
70 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
71 (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
72 CPM_CPPCR_PLLEN; /* enable PLL */
73
74 /* init PLL */
75 writel(cfcr, &cpm->cpccr);
76 writel(plcr1, &cpm->cppcr);
77}
78
79void sdram_init(void)
80{
81 struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
82
83 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
84
85 unsigned int cas_latency_sdmr[2] = {
86 EMC_SDMR_CAS_2,
87 EMC_SDMR_CAS_3,
88 };
89
90 unsigned int cas_latency_dmcr[2] = {
91 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
92 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
93 };
94
95 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
96
97 cpu_clk = CONFIG_SYS_CPU_SPEED;
98 mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
99
100 writel(0, &emc->bcr); /* Disable bus release */
101 writew(0, &emc->rtcsr); /* Disable clock for counting */
102
103 /* Fault DMCR value for mode register setting*/
104#define SDRAM_ROW0 11
105#define SDRAM_COL0 8
106#define SDRAM_BANK40 0
107
108 dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
109 ((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
110 (SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
111 (SDRAM_BW16 << EMC_DMCR_BW_BIT) |
112 EMC_DMCR_EPIN |
113 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
114
115 /* Basic DMCR value */
116 dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
117 ((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
118 (SDRAM_BANK4 << EMC_DMCR_BA_BIT) |
119 (SDRAM_BW16 << EMC_DMCR_BW_BIT) |
120 EMC_DMCR_EPIN |
121 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
122
123 /* SDRAM timimg */
124 ns = 1000000000 / mem_clk;
125 tmp = SDRAM_TRAS / ns;
126 if (tmp < 4)
127 tmp = 4;
128 if (tmp > 11)
129 tmp = 11;
130 dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT;
131 tmp = SDRAM_RCD / ns;
132
133 if (tmp > 3)
134 tmp = 3;
135 dmcr |= tmp << EMC_DMCR_RCD_BIT;
136 tmp = SDRAM_TPC / ns;
137
138 if (tmp > 7)
139 tmp = 7;
140 dmcr |= tmp << EMC_DMCR_TPC_BIT;
141 tmp = SDRAM_TRWL / ns;
142
143 if (tmp > 3)
144 tmp = 3;
145 dmcr |= tmp << EMC_DMCR_TRWL_BIT;
146 tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
147
148 if (tmp > 14)
149 tmp = 14;
150 dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT;
151
152 /* SDRAM mode value */
153 sdmode = EMC_SDMR_BT_SEQ |
154 EMC_SDMR_OM_NORMAL |
155 EMC_SDMR_BL_4 |
156 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
157
158 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
159 writel(dmcr, &emc->dmcr);
160 writeb(0, JZ4740_EMC_SDMR0 | sdmode);
161
162 /* Wait for precharge, > 200us */
163 tmp = (cpu_clk / 1000000) * 1000;
164 while (tmp--)
165 ;
166
167 /* Stage 2. Enable auto-refresh */
168 writel(dmcr | EMC_DMCR_RFSH, &emc->dmcr);
169
170 tmp = SDRAM_TREF / ns;
171 tmp = tmp / 64 + 1;
172 if (tmp > 0xff)
173 tmp = 0xff;
174 writew(tmp, &emc->rtcor);
175 writew(0, &emc->rtcnt);
176 /* Divisor is 64, CKO/64 */
177 writew(EMC_RTCSR_CKS_64, &emc->rtcsr);
178
179 /* Wait for number of auto-refresh cycles */
180 tmp = (cpu_clk / 1000000) * 1000;
181 while (tmp--)
182 ;
183
184 /* Stage 3. Mode Register Set */
185 writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
186 writeb(0, JZ4740_EMC_SDMR0 | sdmode);
187
188 /* Set back to basic DMCR value */
189 writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
190
191 /* everything is ok now */
192}
193
194DECLARE_GLOBAL_DATA_PTR;
195
196void calc_clocks(void)
197{
198 unsigned int pllout;
199 unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
200
201 pllout = __cpm_get_pllout();
202
203 gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
Daniel Schwierzeck97b920d2013-02-12 22:22:12 +0100204 gd->arch.sys_clk = pllout / div[__cpm_get_hdiv()];
205 gd->arch.per_clk = pllout / div[__cpm_get_pdiv()];
Xiangfu Liu80421fc2011-10-12 12:24:06 +0800206 gd->mem_clk = pllout / div[__cpm_get_mdiv()];
Daniel Schwierzeck97b920d2013-02-12 22:22:12 +0100207 gd->arch.dev_clk = CONFIG_SYS_EXTAL;
Xiangfu Liu80421fc2011-10-12 12:24:06 +0800208}
209
210void rtc_init(void)
211{
212 struct jz4740_rtc *rtc = (struct jz4740_rtc *)JZ4740_RTC_BASE;
213
214 while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
215 ;
216 writel(readl(&rtc->rcr) | RTC_RCR_AE, &rtc->rcr); /* enable alarm */
217
218 while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
219 ;
220 writel(0x00007fff, &rtc->rgr); /* type value */
221
222 while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
223 ;
224 writel(0x0000ffe0, &rtc->hwfcr); /* Power on delay 2s */
225
226 while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
227 ;
228 writel(0x00000fe0, &rtc->hrcr); /* reset delay 125ms */
229}
230
231/* U-Boot common routines */
232phys_size_t initdram(int board_type)
233{
234 struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
235 u32 dmcr;
236 u32 rows, cols, dw, banks;
237 ulong size;
238
239 dmcr = readl(&emc->dmcr);
240 rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
241 cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
242 dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
243 banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
244
245 size = (1 << (rows + cols)) * dw * banks;
246
247 return size;
248}