Tom Rini | 4549e78 | 2018-05-06 18:27:01 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 4 | */ |
Patrick Delaunay | eb653ac | 2020-11-06 19:01:29 +0100 | [diff] [blame] | 5 | |
| 6 | #define LOG_CATEGORY LOGC_ARCH |
| 7 | |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 8 | #include <common.h> |
| 9 | #include <clk.h> |
Simon Glass | 9edefc2 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 10 | #include <cpu_func.h> |
Patrick Delaunay | 320d266 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 11 | #include <debug_uart.h> |
Simon Glass | 9fb625c | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 12 | #include <env.h> |
Simon Glass | 691d719 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 13 | #include <init.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 14 | #include <log.h> |
Patrick Delaunay | ade4e04 | 2021-05-07 14:50:35 +0200 | [diff] [blame] | 15 | #include <lmb.h> |
Patrick Delaunay | 7f7deb0 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 16 | #include <misc.h> |
Simon Glass | 90526e9 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 17 | #include <net.h> |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 18 | #include <asm/io.h> |
Patrick Delaunay | bd3f60d | 2020-06-16 18:27:44 +0200 | [diff] [blame] | 19 | #include <asm/arch/bsec.h> |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 20 | #include <asm/arch/stm32.h> |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 21 | #include <asm/arch/sys_proto.h> |
Simon Glass | 401d1c4 | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 22 | #include <asm/global_data.h> |
Patrick Delaunay | 7f7deb0 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 23 | #include <dm/device.h> |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 24 | #include <dm/uclass.h> |
Simon Glass | cd93d62 | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 25 | #include <linux/bitops.h> |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 26 | |
Patrick Delaunay | cda3dcb | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 27 | /* RCC register */ |
| 28 | #define RCC_TZCR (STM32_RCC_BASE + 0x00) |
| 29 | #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) |
| 30 | #define RCC_BDCR (STM32_RCC_BASE + 0x0140) |
| 31 | #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) |
Patrick Delaunay | 59a54e3 | 2019-02-27 17:01:26 +0100 | [diff] [blame] | 32 | #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210) |
Patrick Delaunay | cda3dcb | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 33 | #define RCC_BDCR_VSWRST BIT(31) |
| 34 | #define RCC_BDCR_RTCSRC GENMASK(17, 16) |
| 35 | #define RCC_DBGCFGR_DBGCKEN BIT(8) |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 36 | |
Patrick Delaunay | cda3dcb | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 37 | /* Security register */ |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 38 | #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) |
| 39 | #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) |
| 40 | |
| 41 | #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) |
| 42 | #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) |
| 43 | #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) |
| 44 | |
| 45 | #define TAMP_CR1 (STM32_TAMP_BASE + 0x00) |
| 46 | |
| 47 | #define PWR_CR1 (STM32_PWR_BASE + 0x00) |
Fabien Dessenne | 7bff971 | 2019-10-30 14:38:30 +0100 | [diff] [blame] | 48 | #define PWR_MCUCR (STM32_PWR_BASE + 0x14) |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 49 | #define PWR_CR1_DBP BIT(8) |
Fabien Dessenne | 7bff971 | 2019-10-30 14:38:30 +0100 | [diff] [blame] | 50 | #define PWR_MCUCR_SBF BIT(6) |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 51 | |
Patrick Delaunay | cda3dcb | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 52 | /* DBGMCU register */ |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 53 | #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) |
Patrick Delaunay | cda3dcb | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 54 | #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) |
| 55 | #define DBGMCU_APB4FZ1_IWDG2 BIT(2) |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 56 | #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) |
| 57 | #define DBGMCU_IDC_DEV_ID_SHIFT 0 |
| 58 | #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) |
| 59 | #define DBGMCU_IDC_REV_ID_SHIFT 16 |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 60 | |
Patrick Delaunay | 59a54e3 | 2019-02-27 17:01:26 +0100 | [diff] [blame] | 61 | /* GPIOZ registers */ |
| 62 | #define GPIOZ_SECCFGR 0x54004030 |
| 63 | |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 64 | /* boot interface from Bootrom |
| 65 | * - boot instance = bit 31:16 |
| 66 | * - boot device = bit 15:0 |
| 67 | */ |
| 68 | #define BOOTROM_PARAM_ADDR 0x2FFC0078 |
| 69 | #define BOOTROM_MODE_MASK GENMASK(15, 0) |
| 70 | #define BOOTROM_MODE_SHIFT 0 |
| 71 | #define BOOTROM_INSTANCE_MASK GENMASK(31, 16) |
| 72 | #define BOOTROM_INSTANCE_SHIFT 16 |
| 73 | |
Patrick Delaunay | 35d568f | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 74 | /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ |
| 75 | #define RPN_SHIFT 0 |
| 76 | #define RPN_MASK GENMASK(7, 0) |
| 77 | |
| 78 | /* Package = bit 27:29 of OTP16 |
| 79 | * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm |
| 80 | * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm |
| 81 | * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm |
| 82 | * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm |
| 83 | * - others: Reserved |
| 84 | */ |
| 85 | #define PKG_SHIFT 27 |
| 86 | #define PKG_MASK GENMASK(2, 0) |
| 87 | |
Patrick Delaunay | 7e8471c | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 88 | /* |
| 89 | * early TLB into the .data section so that it not get cleared |
| 90 | * with 16kB allignment (see TTBR0_BASE_ADDR_MASK) |
| 91 | */ |
| 92 | u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); |
| 93 | |
Patrick Delaunay | ade4e04 | 2021-05-07 14:50:35 +0200 | [diff] [blame] | 94 | struct lmb lmb; |
| 95 | |
Patrick Delaunay | cda3dcb | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 96 | #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) |
Patrick Delaunay | 654706b | 2020-04-01 09:07:33 +0200 | [diff] [blame] | 97 | #ifndef CONFIG_TFABOOT |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 98 | static void security_init(void) |
| 99 | { |
| 100 | /* Disable the backup domain write protection */ |
| 101 | /* the protection is enable at each reset by hardware */ |
| 102 | /* And must be disable by software */ |
| 103 | setbits_le32(PWR_CR1, PWR_CR1_DBP); |
| 104 | |
| 105 | while (!(readl(PWR_CR1) & PWR_CR1_DBP)) |
| 106 | ; |
| 107 | |
| 108 | /* If RTC clock isn't enable so this is a cold boot then we need |
| 109 | * to reset the backup domain |
| 110 | */ |
| 111 | if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { |
| 112 | setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); |
| 113 | while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) |
| 114 | ; |
| 115 | clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); |
| 116 | } |
| 117 | |
| 118 | /* allow non secure access in Write/Read for all peripheral */ |
| 119 | writel(GENMASK(25, 0), ETZPC_DECPROT0); |
| 120 | |
| 121 | /* Open SYSRAM for no secure access */ |
| 122 | writel(0x0, ETZPC_TZMA1_SIZE); |
| 123 | |
| 124 | /* enable TZC1 TZC2 clock */ |
| 125 | writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); |
| 126 | |
| 127 | /* Region 0 set to no access by default */ |
| 128 | /* bit 0 / 16 => nsaid0 read/write Enable |
| 129 | * bit 1 / 17 => nsaid1 read/write Enable |
| 130 | * ... |
| 131 | * bit 15 / 31 => nsaid15 read/write Enable |
| 132 | */ |
| 133 | writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); |
| 134 | /* bit 30 / 31 => Secure Global Enable : write/read */ |
| 135 | /* bit 0 / 1 => Region Enable for filter 0/1 */ |
| 136 | writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); |
| 137 | |
| 138 | /* Enable Filter 0 and 1 */ |
| 139 | setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); |
| 140 | |
| 141 | /* RCC trust zone deactivated */ |
| 142 | writel(0x0, RCC_TZCR); |
| 143 | |
| 144 | /* TAMP: deactivate the internal tamper |
| 145 | * Bit 23 ITAMP8E: monotonic counter overflow |
| 146 | * Bit 20 ITAMP5E: RTC calendar overflow |
| 147 | * Bit 19 ITAMP4E: HSE monitoring |
| 148 | * Bit 18 ITAMP3E: LSE monitoring |
| 149 | * Bit 16 ITAMP1E: RTC power domain supply monitoring |
| 150 | */ |
| 151 | writel(0x0, TAMP_CR1); |
Patrick Delaunay | 59a54e3 | 2019-02-27 17:01:26 +0100 | [diff] [blame] | 152 | |
| 153 | /* GPIOZ: deactivate the security */ |
| 154 | writel(BIT(0), RCC_MP_AHB5ENSETR); |
| 155 | writel(0x0, GPIOZ_SECCFGR); |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 156 | } |
Patrick Delaunay | 654706b | 2020-04-01 09:07:33 +0200 | [diff] [blame] | 157 | #endif /* CONFIG_TFABOOT */ |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 158 | |
Patrick Delaunay | cda3dcb | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 159 | /* |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 160 | * Debug init |
Patrick Delaunay | cda3dcb | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 161 | */ |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 162 | static void dbgmcu_init(void) |
| 163 | { |
Patrick Delaunay | bd3f60d | 2020-06-16 18:27:44 +0200 | [diff] [blame] | 164 | /* |
| 165 | * Freeze IWDG2 if Cortex-A7 is in debug mode |
| 166 | * done in TF-A for TRUSTED boot and |
| 167 | * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE |
| 168 | */ |
Patrick Delaunay | 97f7e39 | 2020-07-24 11:13:31 +0200 | [diff] [blame] | 169 | if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) { |
| 170 | setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); |
Patrick Delaunay | bd3f60d | 2020-06-16 18:27:44 +0200 | [diff] [blame] | 171 | setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); |
Patrick Delaunay | 97f7e39 | 2020-07-24 11:13:31 +0200 | [diff] [blame] | 172 | } |
| 173 | } |
| 174 | |
| 175 | void spl_board_init(void) |
| 176 | { |
Patrick Delaunay | 9788708 | 2021-10-11 09:52:48 +0200 | [diff] [blame^] | 177 | struct udevice *dev; |
| 178 | int ret; |
| 179 | |
Patrick Delaunay | 97f7e39 | 2020-07-24 11:13:31 +0200 | [diff] [blame] | 180 | dbgmcu_init(); |
Patrick Delaunay | 9788708 | 2021-10-11 09:52:48 +0200 | [diff] [blame^] | 181 | |
| 182 | /* force probe of BSEC driver to shadow the upper OTP */ |
| 183 | ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev); |
| 184 | if (ret) |
| 185 | log_warning("BSEC probe failed: %d\n", ret); |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 186 | } |
| 187 | #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ |
| 188 | |
Patrick Delaunay | 654706b | 2020-04-01 09:07:33 +0200 | [diff] [blame] | 189 | #if !defined(CONFIG_TFABOOT) && \ |
Patrick Delaunay | abf2678 | 2019-02-12 11:44:39 +0100 | [diff] [blame] | 190 | (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) |
Patrick Delaunay | 7f63c1e | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 191 | /* get bootmode from ROM code boot context: saved in TAMP register */ |
| 192 | static void update_bootmode(void) |
| 193 | { |
| 194 | u32 boot_mode; |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 195 | u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); |
| 196 | u32 bootrom_device, bootrom_instance; |
| 197 | |
Patrick Delaunay | 7f63c1e | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 198 | /* enable TAMP clock = RTCAPBEN */ |
| 199 | writel(BIT(8), RCC_MP_APB5ENSETR); |
| 200 | |
| 201 | /* read bootrom context */ |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 202 | bootrom_device = |
| 203 | (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; |
| 204 | bootrom_instance = |
| 205 | (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; |
| 206 | boot_mode = |
| 207 | ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | |
| 208 | ((bootrom_instance << BOOT_INSTANCE_SHIFT) & |
| 209 | BOOT_INSTANCE_MASK); |
| 210 | |
| 211 | /* save the boot mode in TAMP backup register */ |
| 212 | clrsetbits_le32(TAMP_BOOT_CONTEXT, |
| 213 | TAMP_BOOT_MODE_MASK, |
| 214 | boot_mode << TAMP_BOOT_MODE_SHIFT); |
Patrick Delaunay | 7f63c1e | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 215 | } |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 216 | #endif |
Patrick Delaunay | 7f63c1e | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 217 | |
| 218 | u32 get_bootmode(void) |
| 219 | { |
| 220 | /* read bootmode from TAMP backup register */ |
| 221 | return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >> |
| 222 | TAMP_BOOT_MODE_SHIFT; |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 223 | } |
| 224 | |
| 225 | /* |
Patrick Delaunay | aad8414 | 2021-02-05 13:53:33 +0100 | [diff] [blame] | 226 | * weak function overidde: set the DDR/SYSRAM executable before to enable the |
| 227 | * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc) |
| 228 | */ |
| 229 | void dram_bank_mmu_setup(int bank) |
| 230 | { |
| 231 | struct bd_info *bd = gd->bd; |
| 232 | int i; |
| 233 | phys_addr_t start; |
| 234 | phys_size_t size; |
Patrick Delaunay | ade4e04 | 2021-05-07 14:50:35 +0200 | [diff] [blame] | 235 | bool use_lmb = false; |
| 236 | enum dcache_option option; |
Patrick Delaunay | aad8414 | 2021-02-05 13:53:33 +0100 | [diff] [blame] | 237 | |
| 238 | if (IS_ENABLED(CONFIG_SPL_BUILD)) { |
| 239 | start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); |
| 240 | size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); |
| 241 | } else if (gd->flags & GD_FLG_RELOC) { |
| 242 | /* bd->bi_dram is available only after relocation */ |
| 243 | start = bd->bi_dram[bank].start; |
| 244 | size = bd->bi_dram[bank].size; |
Patrick Delaunay | ade4e04 | 2021-05-07 14:50:35 +0200 | [diff] [blame] | 245 | use_lmb = true; |
Patrick Delaunay | aad8414 | 2021-02-05 13:53:33 +0100 | [diff] [blame] | 246 | } else { |
| 247 | /* mark cacheable and executable the beggining of the DDR */ |
| 248 | start = STM32_DDR_BASE; |
| 249 | size = CONFIG_DDR_CACHEABLE_SIZE; |
| 250 | } |
| 251 | |
| 252 | for (i = start >> MMU_SECTION_SHIFT; |
| 253 | i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); |
Patrick Delaunay | ade4e04 | 2021-05-07 14:50:35 +0200 | [diff] [blame] | 254 | i++) { |
| 255 | option = DCACHE_DEFAULT_OPTION; |
| 256 | if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP)) |
| 257 | option = 0; /* INVALID ENTRY in TLB */ |
| 258 | set_section_dcache(i, option); |
| 259 | } |
Patrick Delaunay | aad8414 | 2021-02-05 13:53:33 +0100 | [diff] [blame] | 260 | } |
| 261 | /* |
Patrick Delaunay | 7e8471c | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 262 | * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage |
| 263 | * MMU/TLB is updated in enable_caches() for U-Boot after relocation |
| 264 | * or is deactivated in U-Boot entry function start.S::cpu_init_cp15 |
| 265 | */ |
| 266 | static void early_enable_caches(void) |
| 267 | { |
| 268 | /* I-cache is already enabled in start.S: cpu_init_cp15 */ |
| 269 | |
| 270 | if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) |
| 271 | return; |
| 272 | |
Patrice Chotard | 23e20b2 | 2021-02-24 13:53:27 +0100 | [diff] [blame] | 273 | if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { |
| 274 | gd->arch.tlb_size = PGTABLE_SIZE; |
| 275 | gd->arch.tlb_addr = (unsigned long)&early_tlb; |
| 276 | } |
Patrick Delaunay | 7e8471c | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 277 | |
Patrick Delaunay | aad8414 | 2021-02-05 13:53:33 +0100 | [diff] [blame] | 278 | /* enable MMU (default configuration) */ |
Patrick Delaunay | 7e8471c | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 279 | dcache_enable(); |
Patrick Delaunay | 7e8471c | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 280 | } |
| 281 | |
| 282 | /* |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 283 | * Early system init |
| 284 | */ |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 285 | int arch_cpu_init(void) |
| 286 | { |
Patrick Delaunay | 320d266 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 287 | u32 boot_mode; |
| 288 | |
Patrick Delaunay | 7e8471c | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 289 | early_enable_caches(); |
| 290 | |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 291 | /* early armv7 timer init: needed for polling */ |
| 292 | timer_init(); |
| 293 | |
| 294 | #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) |
Patrick Delaunay | 654706b | 2020-04-01 09:07:33 +0200 | [diff] [blame] | 295 | #ifndef CONFIG_TFABOOT |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 296 | security_init(); |
Patrick Delaunay | 7f63c1e | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 297 | update_bootmode(); |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 298 | #endif |
Fabien Dessenne | 7bff971 | 2019-10-30 14:38:30 +0100 | [diff] [blame] | 299 | /* Reset Coprocessor state unless it wakes up from Standby power mode */ |
| 300 | if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { |
| 301 | writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); |
| 302 | writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); |
| 303 | } |
Patrick Delaunay | abf2678 | 2019-02-12 11:44:39 +0100 | [diff] [blame] | 304 | #endif |
Patrick Delaunay | 320d266 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 305 | |
Patrick Delaunay | 320d266 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 306 | boot_mode = get_bootmode(); |
| 307 | |
Patrick Delaunay | 5a05af8 | 2021-02-25 13:37:01 +0100 | [diff] [blame] | 308 | if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && |
| 309 | (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) |
Patrick Delaunay | 320d266 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 310 | gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; |
| 311 | #if defined(CONFIG_DEBUG_UART) && \ |
Patrick Delaunay | 654706b | 2020-04-01 09:07:33 +0200 | [diff] [blame] | 312 | !defined(CONFIG_TFABOOT) && \ |
Patrick Delaunay | 320d266 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 313 | (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) |
| 314 | else |
| 315 | debug_uart_init(); |
| 316 | #endif |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 317 | |
| 318 | return 0; |
| 319 | } |
| 320 | |
Patrick Delaunay | cda3dcb | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 321 | void enable_caches(void) |
| 322 | { |
Patrick Delaunay | ade4e04 | 2021-05-07 14:50:35 +0200 | [diff] [blame] | 323 | /* parse device tree when data cache is still activated */ |
| 324 | lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); |
| 325 | |
Patrick Delaunay | 7e8471c | 2020-04-30 16:30:20 +0200 | [diff] [blame] | 326 | /* I-cache is already enabled in start.S: icache_enable() not needed */ |
| 327 | |
| 328 | /* deactivate the data cache, early enabled in arch_cpu_init() */ |
| 329 | dcache_disable(); |
| 330 | /* |
| 331 | * update MMU after relocation and enable the data cache |
| 332 | * warning: the TLB location udpated in board_f.c::reserve_mmu |
| 333 | */ |
Patrick Delaunay | cda3dcb | 2018-03-19 19:09:20 +0100 | [diff] [blame] | 334 | dcache_enable(); |
| 335 | } |
| 336 | |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 337 | static u32 read_idc(void) |
| 338 | { |
Patrick Delaunay | bd3f60d | 2020-06-16 18:27:44 +0200 | [diff] [blame] | 339 | /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */ |
| 340 | if (bsec_dbgswenable()) { |
| 341 | setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 342 | |
Patrick Delaunay | bd3f60d | 2020-06-16 18:27:44 +0200 | [diff] [blame] | 343 | return readl(DBGMCU_IDC); |
| 344 | } |
| 345 | |
| 346 | if (CONFIG_IS_ENABLED(STM32MP15x)) |
| 347 | return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */ |
| 348 | else |
| 349 | return 0x0; |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 350 | } |
| 351 | |
Patrick Delaunay | 7802a44 | 2020-03-18 09:24:48 +0100 | [diff] [blame] | 352 | u32 get_cpu_dev(void) |
| 353 | { |
| 354 | return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; |
| 355 | } |
| 356 | |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 357 | u32 get_cpu_rev(void) |
| 358 | { |
| 359 | return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; |
| 360 | } |
| 361 | |
Patrick Delaunay | 35d568f | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 362 | static u32 get_otp(int index, int shift, int mask) |
| 363 | { |
| 364 | int ret; |
| 365 | struct udevice *dev; |
| 366 | u32 otp = 0; |
| 367 | |
| 368 | ret = uclass_get_device_by_driver(UCLASS_MISC, |
Simon Glass | 65e25be | 2020-12-28 20:34:56 -0700 | [diff] [blame] | 369 | DM_DRIVER_GET(stm32mp_bsec), |
Patrick Delaunay | 35d568f | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 370 | &dev); |
| 371 | |
| 372 | if (!ret) |
| 373 | ret = misc_read(dev, STM32_BSEC_SHADOW(index), |
| 374 | &otp, sizeof(otp)); |
| 375 | |
| 376 | return (otp >> shift) & mask; |
| 377 | } |
| 378 | |
| 379 | /* Get Device Part Number (RPN) from OTP */ |
| 380 | static u32 get_cpu_rpn(void) |
| 381 | { |
| 382 | return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); |
| 383 | } |
| 384 | |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 385 | u32 get_cpu_type(void) |
| 386 | { |
Patrick Delaunay | 7802a44 | 2020-03-18 09:24:48 +0100 | [diff] [blame] | 387 | return (get_cpu_dev() << 16) | get_cpu_rpn(); |
Patrick Delaunay | 35d568f | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | /* Get Package options from OTP */ |
Patrick Delaunay | 24cb458 | 2019-07-05 17:20:13 +0200 | [diff] [blame] | 391 | u32 get_cpu_package(void) |
Patrick Delaunay | 35d568f | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 392 | { |
| 393 | return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 394 | } |
| 395 | |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 396 | static const char * const soc_type[] = { |
| 397 | "????", |
| 398 | "151C", "151A", "151F", "151D", |
| 399 | "153C", "153A", "153F", "153D", |
| 400 | "157C", "157A", "157F", "157D" |
| 401 | }; |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 402 | |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 403 | static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" }; |
| 404 | static const char * const soc_rev[] = { "?", "A", "B", "Z" }; |
| 405 | |
| 406 | static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, |
| 407 | unsigned int *rev) |
| 408 | { |
| 409 | u32 cpu_type = get_cpu_type(); |
| 410 | u32 ct = cpu_type & ~(BIT(7) | BIT(0)); |
| 411 | u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0)); |
| 412 | u32 cp = get_cpu_package(); |
| 413 | |
| 414 | /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */ |
| 415 | switch (ct) { |
| 416 | case CPU_STM32MP151Cxx: |
| 417 | *type = cm + 1; |
Patrick Delaunay | 050fed8 | 2020-02-26 11:26:43 +0100 | [diff] [blame] | 418 | break; |
Patrick Delaunay | 35d568f | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 419 | case CPU_STM32MP153Cxx: |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 420 | *type = cm + 5; |
Patrick Delaunay | 35d568f | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 421 | break; |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 422 | case CPU_STM32MP157Cxx: |
| 423 | *type = cm + 9; |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 424 | break; |
| 425 | default: |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 426 | *type = 0; |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 427 | break; |
| 428 | } |
| 429 | |
Patrick Delaunay | 35d568f | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 430 | /* Package */ |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 431 | switch (cp) { |
Patrick Delaunay | 35d568f | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 432 | case PKG_AA_LBGA448: |
Patrick Delaunay | 35d568f | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 433 | case PKG_AB_LBGA354: |
Patrick Delaunay | 35d568f | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 434 | case PKG_AC_TFBGA361: |
Patrick Delaunay | 35d568f | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 435 | case PKG_AD_TFBGA257: |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 436 | *pkg = cp; |
Patrick Delaunay | 35d568f | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 437 | break; |
| 438 | default: |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 439 | *pkg = 0; |
Patrick Delaunay | 35d568f | 2019-02-27 17:01:13 +0100 | [diff] [blame] | 440 | break; |
| 441 | } |
| 442 | |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 443 | /* Revision */ |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 444 | switch (get_cpu_rev()) { |
| 445 | case CPU_REVA: |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 446 | *rev = 1; |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 447 | break; |
| 448 | case CPU_REVB: |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 449 | *rev = 2; |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 450 | break; |
Patrick Delaunay | cf0818b | 2020-01-28 10:11:06 +0100 | [diff] [blame] | 451 | case CPU_REVZ: |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 452 | *rev = 3; |
Patrick Delaunay | cf0818b | 2020-01-28 10:11:06 +0100 | [diff] [blame] | 453 | break; |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 454 | default: |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 455 | *rev = 0; |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 456 | break; |
| 457 | } |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 458 | } |
Patrick Delaunay | 96583cd | 2018-03-19 19:09:21 +0100 | [diff] [blame] | 459 | |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 460 | void get_soc_name(char name[SOC_NAME_SIZE]) |
| 461 | { |
| 462 | unsigned int type, pkg, rev; |
| 463 | |
| 464 | get_cpu_string_offsets(&type, &pkg, &rev); |
| 465 | |
| 466 | snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", |
| 467 | soc_type[type], soc_pkg[pkg], soc_rev[rev]); |
Patrick Delaunay | ac5e4d8 | 2020-02-12 19:37:43 +0100 | [diff] [blame] | 468 | } |
| 469 | |
| 470 | #if defined(CONFIG_DISPLAY_CPUINFO) |
| 471 | int print_cpuinfo(void) |
| 472 | { |
| 473 | char name[SOC_NAME_SIZE]; |
| 474 | |
| 475 | get_soc_name(name); |
| 476 | printf("CPU: %s\n", name); |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 477 | |
| 478 | return 0; |
| 479 | } |
| 480 | #endif /* CONFIG_DISPLAY_CPUINFO */ |
| 481 | |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 482 | static void setup_boot_mode(void) |
| 483 | { |
Patrick Delaunay | 7f63c1e | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 484 | const u32 serial_addr[] = { |
| 485 | STM32_USART1_BASE, |
| 486 | STM32_USART2_BASE, |
| 487 | STM32_USART3_BASE, |
| 488 | STM32_UART4_BASE, |
| 489 | STM32_UART5_BASE, |
| 490 | STM32_USART6_BASE, |
| 491 | STM32_UART7_BASE, |
| 492 | STM32_UART8_BASE |
| 493 | }; |
Patrick Delaunay | 3c1057c | 2021-07-06 17:19:45 +0200 | [diff] [blame] | 494 | const u32 sdmmc_addr[] = { |
| 495 | STM32_SDMMC1_BASE, |
| 496 | STM32_SDMMC2_BASE, |
| 497 | STM32_SDMMC3_BASE |
| 498 | }; |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 499 | char cmd[60]; |
| 500 | u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); |
| 501 | u32 boot_mode = |
| 502 | (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; |
Patrick Delaunay | e609e13 | 2019-06-21 15:26:39 +0200 | [diff] [blame] | 503 | unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; |
Patrick Delaunay | 9a2ba28 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 504 | u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK); |
Patrick Delaunay | 7f63c1e | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 505 | struct udevice *dev; |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 506 | |
Patrick Delaunay | eb653ac | 2020-11-06 19:01:29 +0100 | [diff] [blame] | 507 | log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n", |
| 508 | __func__, boot_ctx, boot_mode, instance, forced_mode); |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 509 | switch (boot_mode & TAMP_BOOT_DEVICE_MASK) { |
| 510 | case BOOT_SERIAL_UART: |
Patrick Delaunay | 7f63c1e | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 511 | if (instance > ARRAY_SIZE(serial_addr)) |
| 512 | break; |
Patrick Delaunay | f49eb16 | 2021-02-25 13:37:03 +0100 | [diff] [blame] | 513 | /* serial : search associated node in devicetree */ |
Patrick Delaunay | 7f63c1e | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 514 | sprintf(cmd, "serial@%x", serial_addr[instance]); |
Patrick Delaunay | f49eb16 | 2021-02-25 13:37:03 +0100 | [diff] [blame] | 515 | if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) { |
Patrick Delaunay | b9d5e3a | 2021-02-25 13:37:02 +0100 | [diff] [blame] | 516 | /* restore console on error */ |
| 517 | if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL)) |
| 518 | gd->flags &= ~(GD_FLG_SILENT | |
| 519 | GD_FLG_DISABLE_CONSOLE); |
Patrick Delaunay | cbea7b3 | 2021-04-06 09:27:39 +0200 | [diff] [blame] | 520 | log_err("uart%d = %s not found in device tree!\n", |
| 521 | instance + 1, cmd); |
Patrick Delaunay | 7f63c1e | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 522 | break; |
Patrick Delaunay | b9d5e3a | 2021-02-25 13:37:02 +0100 | [diff] [blame] | 523 | } |
Patrick Delaunay | f49eb16 | 2021-02-25 13:37:03 +0100 | [diff] [blame] | 524 | sprintf(cmd, "%d", dev_seq(dev)); |
Patrick Delaunay | 7f63c1e | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 525 | env_set("boot_device", "serial"); |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 526 | env_set("boot_instance", cmd); |
Patrick Delaunay | 7f63c1e | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 527 | |
| 528 | /* restore console on uart when not used */ |
Patrick Delaunay | 5a05af8 | 2021-02-25 13:37:01 +0100 | [diff] [blame] | 529 | if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) { |
Patrick Delaunay | 7f63c1e | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 530 | gd->flags &= ~(GD_FLG_SILENT | |
| 531 | GD_FLG_DISABLE_CONSOLE); |
Patrick Delaunay | cbea7b3 | 2021-04-06 09:27:39 +0200 | [diff] [blame] | 532 | log_info("serial boot with console enabled!\n"); |
Patrick Delaunay | 7f63c1e | 2019-02-27 17:01:12 +0100 | [diff] [blame] | 533 | } |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 534 | break; |
| 535 | case BOOT_SERIAL_USB: |
| 536 | env_set("boot_device", "usb"); |
| 537 | env_set("boot_instance", "0"); |
| 538 | break; |
| 539 | case BOOT_FLASH_SD: |
| 540 | case BOOT_FLASH_EMMC: |
Patrick Delaunay | 3c1057c | 2021-07-06 17:19:45 +0200 | [diff] [blame] | 541 | if (instance > ARRAY_SIZE(sdmmc_addr)) |
| 542 | break; |
| 543 | /* search associated sdmmc node in devicetree */ |
| 544 | sprintf(cmd, "mmc@%x", sdmmc_addr[instance]); |
| 545 | if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) { |
| 546 | printf("mmc%d = %s not found in device tree!\n", |
| 547 | instance, cmd); |
| 548 | break; |
| 549 | } |
| 550 | sprintf(cmd, "%d", dev_seq(dev)); |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 551 | env_set("boot_device", "mmc"); |
| 552 | env_set("boot_instance", cmd); |
| 553 | break; |
| 554 | case BOOT_FLASH_NAND: |
| 555 | env_set("boot_device", "nand"); |
| 556 | env_set("boot_instance", "0"); |
| 557 | break; |
Patrick Delaunay | b664a74 | 2020-03-18 09:22:52 +0100 | [diff] [blame] | 558 | case BOOT_FLASH_SPINAND: |
| 559 | env_set("boot_device", "spi-nand"); |
| 560 | env_set("boot_instance", "0"); |
| 561 | break; |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 562 | case BOOT_FLASH_NOR: |
| 563 | env_set("boot_device", "nor"); |
| 564 | env_set("boot_instance", "0"); |
| 565 | break; |
| 566 | default: |
Patrick Delaunay | 8b71b20 | 2021-07-08 10:53:56 +0200 | [diff] [blame] | 567 | env_set("boot_device", "invalid"); |
| 568 | env_set("boot_instance", ""); |
| 569 | log_err("unexpected boot mode = %x\n", boot_mode); |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 570 | break; |
| 571 | } |
Patrick Delaunay | 9a2ba28 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 572 | |
| 573 | switch (forced_mode) { |
| 574 | case BOOT_FASTBOOT: |
Patrick Delaunay | cbea7b3 | 2021-04-06 09:27:39 +0200 | [diff] [blame] | 575 | log_info("Enter fastboot!\n"); |
Patrick Delaunay | 9a2ba28 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 576 | env_set("preboot", "env set preboot; fastboot 0"); |
| 577 | break; |
| 578 | case BOOT_STM32PROG: |
| 579 | env_set("boot_device", "usb"); |
| 580 | env_set("boot_instance", "0"); |
| 581 | break; |
| 582 | case BOOT_UMS_MMC0: |
| 583 | case BOOT_UMS_MMC1: |
| 584 | case BOOT_UMS_MMC2: |
Patrick Delaunay | cbea7b3 | 2021-04-06 09:27:39 +0200 | [diff] [blame] | 585 | log_info("Enter UMS!\n"); |
Patrick Delaunay | 9a2ba28 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 586 | instance = forced_mode - BOOT_UMS_MMC0; |
| 587 | sprintf(cmd, "env set preboot; ums 0 mmc %d", instance); |
| 588 | env_set("preboot", cmd); |
| 589 | break; |
| 590 | case BOOT_RECOVERY: |
| 591 | env_set("preboot", "env set preboot; run altbootcmd"); |
| 592 | break; |
| 593 | case BOOT_NORMAL: |
| 594 | break; |
| 595 | default: |
Patrick Delaunay | eb653ac | 2020-11-06 19:01:29 +0100 | [diff] [blame] | 596 | log_debug("unexpected forced boot mode = %x\n", forced_mode); |
Patrick Delaunay | 9a2ba28 | 2019-02-27 17:01:20 +0100 | [diff] [blame] | 597 | break; |
| 598 | } |
| 599 | |
| 600 | /* clear TAMP for next reboot */ |
| 601 | clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL); |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 602 | } |
| 603 | |
Patrick Delaunay | 7f7deb0 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 604 | /* |
| 605 | * If there is no MAC address in the environment, then it will be initialized |
| 606 | * (silently) from the value in the OTP. |
| 607 | */ |
Marek Vasut | e71b9a6 | 2019-12-18 16:52:19 +0100 | [diff] [blame] | 608 | __weak int setup_mac_address(void) |
Patrick Delaunay | 7f7deb0 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 609 | { |
| 610 | #if defined(CONFIG_NET) |
| 611 | int ret; |
| 612 | int i; |
| 613 | u32 otp[2]; |
| 614 | uchar enetaddr[6]; |
| 615 | struct udevice *dev; |
| 616 | |
| 617 | /* MAC already in environment */ |
| 618 | if (eth_env_get_enetaddr("ethaddr", enetaddr)) |
| 619 | return 0; |
| 620 | |
| 621 | ret = uclass_get_device_by_driver(UCLASS_MISC, |
Simon Glass | 65e25be | 2020-12-28 20:34:56 -0700 | [diff] [blame] | 622 | DM_DRIVER_GET(stm32mp_bsec), |
Patrick Delaunay | 7f7deb0 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 623 | &dev); |
| 624 | if (ret) |
| 625 | return ret; |
| 626 | |
Patrick Delaunay | 17f1f9b | 2019-02-27 17:01:29 +0100 | [diff] [blame] | 627 | ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), |
Patrick Delaunay | 7f7deb0 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 628 | otp, sizeof(otp)); |
Simon Glass | 8729b1a | 2018-11-06 15:21:39 -0700 | [diff] [blame] | 629 | if (ret < 0) |
Patrick Delaunay | 7f7deb0 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 630 | return ret; |
| 631 | |
| 632 | for (i = 0; i < 6; i++) |
| 633 | enetaddr[i] = ((uint8_t *)&otp)[i]; |
| 634 | |
| 635 | if (!is_valid_ethaddr(enetaddr)) { |
Patrick Delaunay | eb653ac | 2020-11-06 19:01:29 +0100 | [diff] [blame] | 636 | log_err("invalid MAC address in OTP %pM\n", enetaddr); |
Patrick Delaunay | 7f7deb0 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 637 | return -EINVAL; |
| 638 | } |
Patrick Delaunay | eb653ac | 2020-11-06 19:01:29 +0100 | [diff] [blame] | 639 | log_debug("OTP MAC address = %pM\n", enetaddr); |
Patrick Delaunay | cf8df34 | 2020-04-07 16:07:46 +0200 | [diff] [blame] | 640 | ret = eth_env_set_enetaddr("ethaddr", enetaddr); |
| 641 | if (ret) |
Patrick Delaunay | eb653ac | 2020-11-06 19:01:29 +0100 | [diff] [blame] | 642 | log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret); |
Patrick Delaunay | 7f7deb0 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 643 | #endif |
| 644 | |
| 645 | return 0; |
| 646 | } |
| 647 | |
| 648 | static int setup_serial_number(void) |
| 649 | { |
| 650 | char serial_string[25]; |
| 651 | u32 otp[3] = {0, 0, 0 }; |
| 652 | struct udevice *dev; |
| 653 | int ret; |
| 654 | |
| 655 | if (env_get("serial#")) |
| 656 | return 0; |
| 657 | |
| 658 | ret = uclass_get_device_by_driver(UCLASS_MISC, |
Simon Glass | 65e25be | 2020-12-28 20:34:56 -0700 | [diff] [blame] | 659 | DM_DRIVER_GET(stm32mp_bsec), |
Patrick Delaunay | 7f7deb0 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 660 | &dev); |
| 661 | if (ret) |
| 662 | return ret; |
| 663 | |
Patrick Delaunay | 17f1f9b | 2019-02-27 17:01:29 +0100 | [diff] [blame] | 664 | ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL), |
Patrick Delaunay | 7f7deb0 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 665 | otp, sizeof(otp)); |
Simon Glass | 8729b1a | 2018-11-06 15:21:39 -0700 | [diff] [blame] | 666 | if (ret < 0) |
Patrick Delaunay | 7f7deb0 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 667 | return ret; |
| 668 | |
Patrick Delaunay | 8983ba2 | 2019-02-27 17:01:25 +0100 | [diff] [blame] | 669 | sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]); |
Patrick Delaunay | 7f7deb0 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 670 | env_set("serial#", serial_string); |
| 671 | |
| 672 | return 0; |
| 673 | } |
| 674 | |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 675 | static void setup_soc_type_pkg_rev(void) |
| 676 | { |
| 677 | unsigned int type, pkg, rev; |
| 678 | |
| 679 | get_cpu_string_offsets(&type, &pkg, &rev); |
| 680 | |
| 681 | env_set("soc_type", soc_type[type]); |
| 682 | env_set("soc_pkg", soc_pkg[pkg]); |
| 683 | env_set("soc_rev", soc_rev[rev]); |
| 684 | } |
| 685 | |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 686 | int arch_misc_init(void) |
| 687 | { |
| 688 | setup_boot_mode(); |
Patrick Delaunay | 7f7deb0 | 2018-05-17 15:24:07 +0200 | [diff] [blame] | 689 | setup_mac_address(); |
| 690 | setup_serial_number(); |
Marek Vasut | 2c2d7d6 | 2021-03-31 14:15:09 +0200 | [diff] [blame] | 691 | setup_soc_type_pkg_rev(); |
Patrick Delaunay | 08772f6 | 2018-03-20 10:54:53 +0100 | [diff] [blame] | 692 | |
| 693 | return 0; |
| 694 | } |