| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> |
| 4 | * |
| 5 | * Authors: Igor Grinberg <grinberg@compulab.co.il> |
| Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/arch/sys_proto.h> |
| 10 | #include <asm/arch/mux.h> |
| 11 | #include <asm/io.h> |
| 12 | |
| 13 | void set_muxconf_regs(void) |
| 14 | { |
| 15 | /* SDRC */ |
| 16 | MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); |
| 17 | MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); |
| 18 | MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); |
| 19 | MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); |
| 20 | MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); |
| 21 | MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); |
| 22 | MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); |
| 23 | MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); |
| 24 | MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); |
| 25 | MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); |
| 26 | MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); |
| 27 | MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); |
| 28 | MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); |
| 29 | MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); |
| 30 | MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); |
| 31 | MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); |
| 32 | MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); |
| 33 | MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); |
| 34 | MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); |
| 35 | MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); |
| 36 | MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); |
| 37 | MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); |
| 38 | MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); |
| 39 | MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); |
| 40 | MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); |
| 41 | MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); |
| 42 | MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); |
| 43 | MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); |
| 44 | MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); |
| 45 | MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); |
| 46 | MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); |
| 47 | MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); |
| 48 | MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); |
| 49 | MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); |
| 50 | MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); |
| 51 | MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); |
| 52 | MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); |
| 53 | MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); |
| 54 | MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); |
| 55 | |
| 56 | /* GPMC */ |
| 57 | MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); |
| 58 | MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); |
| 59 | MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); |
| 60 | MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); |
| 61 | MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); |
| 62 | MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); |
| 63 | MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); |
| 64 | MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); |
| 65 | MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); |
| 66 | MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); |
| 67 | MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); |
| 68 | MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); |
| 69 | MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); |
| 70 | MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); |
| 71 | MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); |
| 72 | MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); |
| 73 | MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); |
| 74 | MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); |
| 75 | MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); |
| 76 | MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); |
| 77 | MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); |
| 78 | MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); |
| 79 | MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); |
| 80 | MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); |
| 81 | MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); |
| 82 | MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); |
| 83 | MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); |
| 84 | |
| Igor Grinberg | a8a78c7 | 2014-11-03 11:32:26 +0200 | [diff] [blame] | 85 | /* SB-T35 Ethernet */ |
| 86 | MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); |
| Igor Grinberg | 40bbd52 | 2014-11-03 11:32:27 +0200 | [diff] [blame] | 87 | /* DVI enable */ |
| 88 | MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/ |
| 89 | /* DataImage backlight */ |
| 90 | MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ |
| Igor Grinberg | a8a78c7 | 2014-11-03 11:32:26 +0200 | [diff] [blame] | 91 | |
| Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 92 | /* SB-T35 SD/MMC WP GPIO59 */ |
| 93 | MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/ |
| 94 | MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); |
| 95 | MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); |
| 96 | MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); |
| 97 | MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); |
| 98 | /* SB-T35 Audio Enable GPIO61 */ |
| 99 | MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/ |
| 100 | MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); |
| 101 | MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); |
| Igor Grinberg | a8a78c7 | 2014-11-03 11:32:26 +0200 | [diff] [blame] | 102 | /* SB-T35 Ethernet IRQ GPIO65 */ |
| 103 | MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/ |
| Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 104 | |
| 105 | /* UART3 Console */ |
| 106 | MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); |
| 107 | MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); |
| 108 | /* RTC V3020 nCS GPIO163 */ |
| 109 | MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/ |
| Igor Grinberg | a8a78c7 | 2014-11-03 11:32:26 +0200 | [diff] [blame] | 110 | /* SB-T35 Ethernet nRESET GPIO164 */ |
| 111 | MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/ |
| Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 112 | |
| 113 | /* SB-T35 SD/MMC CD GPIO144 */ |
| 114 | MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/ |
| 115 | /* WIFI nRESET GPIO145 */ |
| 116 | MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/ |
| Igor Grinberg | 011f5c1 | 2014-11-03 11:32:25 +0200 | [diff] [blame] | 117 | /* USB1 PHY Reset GPIO 146 */ |
| 118 | MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/ |
| 119 | /* USB2 PHY Reset GPIO 147 */ |
| 120 | MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/ |
| Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 121 | |
| 122 | /* MMC1 */ |
| Dmitry Lifshitz | 63bb759 | 2015-09-08 09:50:01 +0300 | [diff] [blame] | 123 | MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)); |
| 124 | MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)); |
| 125 | MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)); |
| 126 | MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)); |
| 127 | MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)); |
| 128 | MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)); |
| Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 129 | |
| Igor Grinberg | 40bbd52 | 2014-11-03 11:32:27 +0200 | [diff] [blame] | 130 | /* DSS */ |
| 131 | MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); |
| 132 | MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); |
| 133 | MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); |
| 134 | MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); |
| 135 | MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); |
| 136 | MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); |
| 137 | MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); |
| 138 | MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); |
| 139 | MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); |
| 140 | MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); |
| 141 | MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); |
| 142 | MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); |
| 143 | MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); |
| 144 | MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); |
| 145 | MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); |
| 146 | MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); |
| 147 | MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); |
| 148 | MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); |
| 149 | MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); |
| 150 | MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); |
| 151 | MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); |
| 152 | MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); |
| 153 | MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); |
| 154 | MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); |
| 155 | MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); |
| 156 | MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); |
| 157 | MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); |
| 158 | MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); |
| 159 | |
| Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 160 | /* I2C */ |
| 161 | MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); |
| 162 | MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); |
| 163 | MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); |
| 164 | MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); |
| 165 | |
| Igor Grinberg | 011f5c1 | 2014-11-03 11:32:25 +0200 | [diff] [blame] | 166 | /* SB-T35 USB HUB Reset GPIO98 */ |
| 167 | MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/ |
| 168 | /* CM-T3517 USB HUB Reset GPIO152 */ |
| 169 | MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/ |
| 170 | |
| Igor Grinberg | a8a78c7 | 2014-11-03 11:32:26 +0200 | [diff] [blame] | 171 | /* RMII */ |
| 172 | MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0)); |
| 173 | MUX_VAL(CP(RMII_MDIO_CLK), (M0)); |
| 174 | MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0)); |
| 175 | MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0)); |
| 176 | MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0)); |
| 177 | MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0)); |
| 178 | MUX_VAL(CP(RMII_TXD0), (IDIS | M0)); |
| 179 | MUX_VAL(CP(RMII_TXD1), (IDIS | M0)); |
| 180 | MUX_VAL(CP(RMII_TXEN), (IDIS | M0)); |
| 181 | MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0)); |
| 182 | |
| Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 183 | /* Green LED GPIO186 */ |
| 184 | MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/ |
| 185 | |
| Igor Grinberg | 40bbd52 | 2014-11-03 11:32:27 +0200 | [diff] [blame] | 186 | /* SPI */ |
| 187 | MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ |
| 188 | MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ |
| 189 | MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ |
| 190 | MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ |
| 191 | /* LCD reset GPIO157 */ |
| 192 | MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ |
| 193 | |
| Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 194 | /* RTC V3020 CS Enable GPIO160 */ |
| 195 | MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/ |
| Igor Grinberg | 40bbd52 | 2014-11-03 11:32:27 +0200 | [diff] [blame] | 196 | /* SB-T35 LVDS Transmitter SHDN GPIO162 */ |
| 197 | MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/ |
| Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 198 | |
| Igor Grinberg | 011f5c1 | 2014-11-03 11:32:25 +0200 | [diff] [blame] | 199 | /* USB0 - mUSB */ |
| 200 | MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)); |
| 201 | /* USB1 EHCI */ |
| 202 | MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ |
| 203 | MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ |
| 204 | MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ |
| 205 | MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ |
| 206 | MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ |
| 207 | MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ |
| 208 | MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ |
| 209 | MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ |
| 210 | MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ |
| 211 | MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ |
| 212 | MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ |
| 213 | MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ |
| 214 | /* USB2 EHCI */ |
| 215 | MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ |
| 216 | MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ |
| 217 | MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ |
| 218 | MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ |
| 219 | MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ |
| 220 | MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ |
| 221 | MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ |
| 222 | MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ |
| 223 | MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ |
| 224 | MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ |
| 225 | MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ |
| 226 | MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ |
| 227 | |
| Igor Grinberg | b09bf72 | 2014-11-05 14:25:35 +0200 | [diff] [blame] | 228 | /* SYS_BOOT */ |
| 229 | MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/ |
| 230 | MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/ |
| 231 | MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/ |
| 232 | MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/ |
| 233 | MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/ |
| 234 | MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/ |
| 235 | } |