| Weijie Gao | 6bd888b | 2020-04-21 09:28:49 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2020 MediaTek Inc. |
| 4 | * |
| 5 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_MT7628_H |
| 9 | #define __CONFIG_MT7628_H |
| 10 | |
| Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 11 | #define CFG_SYS_SDRAM_BASE 0x80000000 |
| Weijie Gao | 6bd888b | 2020-04-21 09:28:49 +0200 | [diff] [blame] | 12 | |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 13 | #define CFG_SYS_INIT_SP_OFFSET 0x80000 |
| Weijie Gao | 6bd888b | 2020-04-21 09:28:49 +0200 | [diff] [blame] | 14 | |
| Weijie Gao | 6bd888b | 2020-04-21 09:28:49 +0200 | [diff] [blame] | 15 | /* Serial SPL */ |
| Simon Glass | 2a73606 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 16 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) |
| Tom Rini | 9109213 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 17 | #define CFG_SYS_NS16550_CLK 40000000 |
| 18 | #define CFG_SYS_NS16550_COM1 0xb0000c00 |
| Weijie Gao | 6bd888b | 2020-04-21 09:28:49 +0200 | [diff] [blame] | 19 | #endif |
| 20 | |
| 21 | /* Serial common */ |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 22 | #define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ |
| Weijie Gao | 6bd888b | 2020-04-21 09:28:49 +0200 | [diff] [blame] | 23 | 230400, 460800, 921600 } |
| 24 | |
| 25 | /* SPL */ |
| Weijie Gao | 6bd888b | 2020-04-21 09:28:49 +0200 | [diff] [blame] | 26 | |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 27 | #define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE |
| Weijie Gao | 6bd888b | 2020-04-21 09:28:49 +0200 | [diff] [blame] | 28 | |
| 29 | /* Dummy value */ |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 30 | #define CFG_SYS_UBOOT_BASE 0 |
| Weijie Gao | 6bd888b | 2020-04-21 09:28:49 +0200 | [diff] [blame] | 31 | |
| 32 | #endif /* __CONFIG_MT7628_H */ |