blob: b846afcc0b517d9427be8fb1b87cfbb940886d62 [file] [log] [blame]
stroesea20b27a2004-12-16 18:05:42 +00001/*
Matthias Fuchs1c686672008-04-21 14:42:17 +02002 * (C) Copyright 2005-2008
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
stroesea20b27a2004-12-16 18:05:42 +00005 * (C) Copyright 2001-2004
6 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * board/config.h - configuration options, board specific
29 */
stroesea20b27a2004-12-16 18:05:42 +000030#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
stroesea20b27a2004-12-16 18:05:42 +000037#define CONFIG_405GP 1 /* This is a PPC405 CPU */
38#define CONFIG_4xx 1 /* ...member of PPC4xx family */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020039#define CONFIG_APCG405 1 /* ...on a APC405 board */
stroesea20b27a2004-12-16 18:05:42 +000040
Wolfgang Denk2ae18242010-10-06 09:05:45 +020041#define CONFIG_SYS_TEXT_BASE 0xFFF80000
42
stroesea20b27a2004-12-16 18:05:42 +000043#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
Matthias Fuchs1c686672008-04-21 14:42:17 +020044#define CONFIG_BOARD_EARLY_INIT_R 1
stroesea20b27a2004-12-16 18:05:42 +000045#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
46
47#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
48
stroese04e93ec2005-04-13 10:06:07 +000049#define CONFIG_BOARD_TYPES 1 /* support board types */
50
Matthias Fuchs1c686672008-04-21 14:42:17 +020051#define CONFIG_BAUDRATE 115200
52#define CONFIG_BOOTDELAY 1 /* autoboot after 3 seconds */
Matthias Fuchs8e048c42008-04-25 12:01:39 +020053#define CONFIG_BOOTCOUNT_LIMIT 1
stroesea20b27a2004-12-16 18:05:42 +000054
55#undef CONFIG_BOOTARGS
Matthias Fuchs1c686672008-04-21 14:42:17 +020056
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_USB_LOAD_COMMAND "fatload usb 0 200000 pImage;" \
Matthias Fuchs1c686672008-04-21 14:42:17 +020058 "fatload usb 0 300000 pImage.initrd"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_USB_SELF_COMMAND "usb start;run usb_load;usb stop;" \
Matthias Fuchs1c686672008-04-21 14:42:17 +020060 "run ramargs addip addcon usbargs;" \
61 "bootm 200000 300000"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_USB_ARGS "setenv bootargs $(bootargs) usbboot=1"
63#define CONFIG_SYS_BOOTLIMIT "3"
64#define CONFIG_SYS_ALT_BOOTCOMMAND "run usb_self;reset"
Matthias Fuchs1c686672008-04-21 14:42:17 +020065
66#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roeseb789cb42008-04-22 14:06:42 +020067 "hostname=abg405\0" \
68 "bd_type=abg405\0" \
Matthias Fuchs1c686672008-04-21 14:42:17 +020069 "serial#=AA0000\0" \
Stefan Roeseb789cb42008-04-22 14:06:42 +020070 "kernel_addr=fe000000\0" \
71 "ramdisk_addr=fe100000\0" \
72 "ramargs=setenv bootargs root=/dev/ram rw\0" \
73 "nfsargs=setenv bootargs root=/dev/nfs rw " \
74 "nfsroot=$(serverip):$(rootpath)\0" \
75 "addip=setenv bootargs $(bootargs) " \
76 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
77 ":$(hostname)::off panic=1\0" \
78 "addcon=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)" \
79 " $(optargs)\0" \
80 "flash_self=run ramargs addip addcon;" \
81 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
82 "net_nfs=tftp 200000 $(img);run nfsargs addip addcon;" \
83 "bootm\0" \
84 "rootpath=/tftpboot/abg405/target_root\0" \
85 "img=/tftpboot/abg405/pImage\0" \
86 "load=tftp 100000 /tftpboot/abg405/u-boot.bin\0" \
87 "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
88 "cp.b 100000 fff80000 80000\0" \
89 "ipaddr=10.0.111.111\0" \
90 "netmask=255.255.0.0\0" \
91 "serverip=10.0.0.190\0" \
92 "splashimage=ffe80000\0" \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093 "usb_load="CONFIG_SYS_USB_LOAD_COMMAND"\0" \
94 "usb_self="CONFIG_SYS_USB_SELF_COMMAND"\0" \
95 "usbargs="CONFIG_SYS_USB_ARGS"\0" \
96 "bootlimit="CONFIG_SYS_BOOTLIMIT"\0" \
97 "altbootcmd="CONFIG_SYS_ALT_BOOTCOMMAND"\0" \
Stefan Roeseb789cb42008-04-22 14:06:42 +020098 ""
Matthias Fuchs8e048c42008-04-25 12:01:39 +020099#define CONFIG_BOOTCOMMAND "run flash_self;reset"
Matthias Fuchs1c686672008-04-21 14:42:17 +0200100
101#define CONFIG_ETHADDR 00:02:27:8e:00:00
stroesea20b27a2004-12-16 18:05:42 +0000102
103#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroesea20b27a2004-12-16 18:05:42 +0000105
Matthias Fuchs1c686672008-04-21 14:42:17 +0200106#define CONFIG_NET_MULTI 1
107#undef CONFIG_HAS_ETH1
108
Matthias Fuchs38570b22010-08-25 17:02:28 +0200109#define CONFIG_PPC4xx_EMAC
stroesea20b27a2004-12-16 18:05:42 +0000110#define CONFIG_MII 1 /* MII PHY management */
Matthias Fuchs1c686672008-04-21 14:42:17 +0200111#define CONFIG_PHY_ADDR 0 /* PHY address */
112#define CONFIG_LXT971_NO_SLEEP 1
113#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
stroesea20b27a2004-12-16 18:05:42 +0000114
115#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
116
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500117/*
Jon Loeliger11799432007-07-10 09:02:57 -0500118 * BOOTP options
119 */
120#define CONFIG_BOOTP_BOOTFILESIZE
121#define CONFIG_BOOTP_BOOTPATH
122#define CONFIG_BOOTP_GATEWAY
123#define CONFIG_BOOTP_HOSTNAME
124
Jon Loeliger11799432007-07-10 09:02:57 -0500125/*
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500126 * Command line configuration.
127 */
128#include <config_cmd_default.h>
129
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500130#define CONFIG_CMD_DATE
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200131#define CONFIG_CMD_DHCP
Wolfgang Denk5728be32007-08-06 01:01:49 +0200132#define CONFIG_CMD_EEPROM
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200133#define CONFIG_CMD_ELF
134#define CONFIG_CMD_FAT
135#define CONFIG_CMD_I2C
136#define CONFIG_CMD_IDE
137#define CONFIG_CMD_IRQ
138#define CONFIG_CMD_MII
139#define CONFIG_CMD_PCI
140#define CONFIG_CMD_PING
141#define CONFIG_CMD_SOURCE
Matthias Fuchs1c686672008-04-21 14:42:17 +0200142#define CONFIG_CMD_USB
stroesea20b27a2004-12-16 18:05:42 +0000143
144#define CONFIG_MAC_PARTITION
145#define CONFIG_DOS_PARTITION
146
147#define CONFIG_SUPPORT_VFAT
148
Matthias Fuchs1c686672008-04-21 14:42:17 +0200149#define CONFIG_AUTO_UPDATE 1 /* autoupdate via CF or USB */
stroesea20b27a2004-12-16 18:05:42 +0000150
Matthias Fuchs1c686672008-04-21 14:42:17 +0200151#undef CONFIG_WATCHDOG /* watchdog disabled */
stroesea20b27a2004-12-16 18:05:42 +0000152
Matthias Fuchs1c686672008-04-21 14:42:17 +0200153#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
Matthias Fuchs1c686672008-04-21 14:42:17 +0200155
156#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroesea20b27a2004-12-16 18:05:42 +0000157
158/*
159 * Miscellaneous configurable options
160 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_LONGHELP /* undef to save memory */
162#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Matthias Fuchs1c686672008-04-21 14:42:17 +0200163#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
stroesea20b27a2004-12-16 18:05:42 +0000164
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500165#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000167#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000169#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
171#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
172#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroesea20b27a2004-12-16 18:05:42 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroesea20b27a2004-12-16 18:05:42 +0000177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
179#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroesea20b27a2004-12-16 18:05:42 +0000180
Stefan Roese550650d2010-09-20 16:05:31 +0200181#define CONFIG_CONS_INDEX 1 /* Use UART0 */
182#define CONFIG_SYS_NS16550
183#define CONFIG_SYS_NS16550_SERIAL
184#define CONFIG_SYS_NS16550_REG_SIZE 1
185#define CONFIG_SYS_NS16550_CLK get_serial_clock()
186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
stroesea20b27a2004-12-16 18:05:42 +0000188
189/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_BAUDRATE_TABLE \
Matthias Fuchs1c686672008-04-21 14:42:17 +0200191 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
wdenkefe2a4d2004-12-16 21:44:03 +0000192 57600, 115200, 230400, 460800, 921600 }
stroesea20b27a2004-12-16 18:05:42 +0000193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
195#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroesea20b27a2004-12-16 18:05:42 +0000196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
stroesea20b27a2004-12-16 18:05:42 +0000198
199#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
200
201/* Only interrupt boot if space is pressed */
202/* If a long serial cable is connected but */
203/* other end is dead, garbage will be read */
Matthias Fuchs1c686672008-04-21 14:42:17 +0200204#define CONFIG_AUTOBOOT_KEYED 1
Wolfgang Denkc37207d2008-07-16 16:38:59 +0200205#define CONFIG_AUTOBOOT_PROMPT \
206 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Matthias Fuchs1c686672008-04-21 14:42:17 +0200207#undef CONFIG_AUTOBOOT_DELAY_STR
stroesea20b27a2004-12-16 18:05:42 +0000208#define CONFIG_AUTOBOOT_STOP_STR " "
209
Matthias Fuchs1c686672008-04-21 14:42:17 +0200210#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroesea20b27a2004-12-16 18:05:42 +0000211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroesea20b27a2004-12-16 18:05:42 +0000213
Matthias Fuchs1c686672008-04-21 14:42:17 +0200214/*
stroesea20b27a2004-12-16 18:05:42 +0000215 * PCI stuff
stroesea20b27a2004-12-16 18:05:42 +0000216 */
Matthias Fuchs1c686672008-04-21 14:42:17 +0200217#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
218#define PCI_HOST_FORCE 1 /* configure as pci host */
219#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroesea20b27a2004-12-16 18:05:42 +0000220
Matthias Fuchs1c686672008-04-21 14:42:17 +0200221#define CONFIG_PCI /* include pci support */
222#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
stroesea20b27a2004-12-16 18:05:42 +0000223#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenkefe2a4d2004-12-16 21:44:03 +0000224 /* resource configuration */
stroesea20b27a2004-12-16 18:05:42 +0000225
Matthias Fuchs1c686672008-04-21 14:42:17 +0200226#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
227#define CONFIG_PCI_SKIP_HOST_BRIDGE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
229#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
230#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
231#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
232#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
233#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
234#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
235#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
236#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroesea20b27a2004-12-16 18:05:42 +0000237
Matthias Fuchs1c686672008-04-21 14:42:17 +0200238/*
stroesea20b27a2004-12-16 18:05:42 +0000239 * IDE/ATA stuff
stroesea20b27a2004-12-16 18:05:42 +0000240 */
Matthias Fuchs1c686672008-04-21 14:42:17 +0200241#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
242#undef CONFIG_IDE_LED /* no led for ide supported */
243#define CONFIG_IDE_RESET 1 /* reset for ide supported */
stroesea20b27a2004-12-16 18:05:42 +0000244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
246#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS) /* max. 1 drives per IDE bus */
stroesea20b27a2004-12-16 18:05:42 +0000247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
249#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
stroesea20b27a2004-12-16 18:05:42 +0000250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
252#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */
253#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
stroesea20b27a2004-12-16 18:05:42 +0000254
Matthias Fuchs1c686672008-04-21 14:42:17 +0200255/*
stroesea20b27a2004-12-16 18:05:42 +0000256 * Start addresses for the final memory configuration
257 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroesea20b27a2004-12-16 18:05:42 +0000259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_SDRAM_BASE 0x00000000
261#define CONFIG_SYS_MONITOR_BASE 0xFFF80000
262#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
263#define CONFIG_SYS_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */
stroesea20b27a2004-12-16 18:05:42 +0000264
265/*
266 * For booting Linux, the board info and command line data
267 * have to be in the first 8 MB of memory, since this is
268 * the maximum mapped by the Linux kernel during initialization.
269 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Init. Memory map for Linux */
stroesea20b27a2004-12-16 18:05:42 +0000271
Matthias Fuchs1c686672008-04-21 14:42:17 +0200272/*
stroesea20b27a2004-12-16 18:05:42 +0000273 * FLASH organization
274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_FLASH_BASE 0xFE000000
276#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200277#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
280#define CONFIG_SYS_FLASH_QUIET_TEST 1
281#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
282#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
283#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { \
Matthias Fuchs1c686672008-04-21 14:42:17 +0200284 {0xfe000000, 0x500000}, \
285 {0xffe80000, 0x180000} \
286 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
288#define CONFIG_SYS_FLASH_BANKS_LIST { \
289 CONFIG_SYS_FLASH_BASE, \
290 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT \
Matthias Fuchs1c686672008-04-21 14:42:17 +0200291 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroesea20b27a2004-12-16 18:05:42 +0000293
Matthias Fuchs1c686672008-04-21 14:42:17 +0200294/*
stroesea20b27a2004-12-16 18:05:42 +0000295 * Environment Variable setup
296 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200297#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200298#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the */
Matthias Fuchs1c686672008-04-21 14:42:17 +0200299 /* beginning of the EEPROM */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200300#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
Matthias Fuchs1c686672008-04-21 14:42:17 +0200301#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting vendor vars */
stroesea20b27a2004-12-16 18:05:42 +0000302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
304#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
stroesea20b27a2004-12-16 18:05:42 +0000305
Matthias Fuchs1c686672008-04-21 14:42:17 +0200306/*
stroesea20b27a2004-12-16 18:05:42 +0000307 * I2C EEPROM (CAT24WC16) for environment
308 */
309#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed3061c62010-04-28 11:09:59 +0200310#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
312#define CONFIG_SYS_I2C_SLAVE 0x7F
stroesea20b27a2004-12-16 18:05:42 +0000313
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
315#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Matthias Fuchs1c686672008-04-21 14:42:17 +0200316/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
318#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
stroesea20b27a2004-12-16 18:05:42 +0000319 /* 16 byte page write mode using*/
Matthias Fuchs1c686672008-04-21 14:42:17 +0200320 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroesea20b27a2004-12-16 18:05:42 +0000322
Matthias Fuchs1c686672008-04-21 14:42:17 +0200323/*
stroesea20b27a2004-12-16 18:05:42 +0000324 * External Bus Controller (EBC) Setup
325 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define FLASH0_BA (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT) /* FLASH 0 BA */
327#define FLASH1_BA CONFIG_SYS_FLASH_BASE /* FLASH 1 Base Address */
Matthias Fuchs1c686672008-04-21 14:42:17 +0200328#define CAN_BA 0xF0000000 /* CAN Base Address */
329#define DUART0_BA 0xF0000400 /* DUART Base Address */
330#define DUART1_BA 0xF0000408 /* DUART Base Address */
331#define RTC_BA 0xF0000500 /* RTC Base Address */
332#define PS2_BA 0xF0000600 /* PS/2 Base Address */
333#define CF_BA 0xF0100000 /* CompactFlash Base Address */
334#define FPGA_BA 0xF0100100 /* FPGA internal Base Address */
335#define FUJI_BA 0xF0100200 /* Fuji internal Base Address */
336#define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */
337#define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */
338#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
stroesea20b27a2004-12-16 18:05:42 +0000339
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */
stroesea20b27a2004-12-16 18:05:42 +0000341
Matthias Fuchs1c686672008-04-21 14:42:17 +0200342/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_EBC_PB0AP 0x92015480
344#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
345#define CONFIG_SYS_EBC_PB0AP_HWREV8 CONFIG_SYS_EBC_PB0AP
346#define CONFIG_SYS_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */
stroesea20b27a2004-12-16 18:05:42 +0000347
Matthias Fuchs1c686672008-04-21 14:42:17 +0200348/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_EBC_PB1AP 0x92015480
350#define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
stroesea20b27a2004-12-16 18:05:42 +0000351
352/* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
354#define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000355
356/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
358#define CONFIG_SYS_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000359
360/* Memory Bank 4 (PCMCIA Slot 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_EBC_PB4AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
362#define CONFIG_SYS_EBC_PB4CR PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
stroesea20b27a2004-12-16 18:05:42 +0000363
364/* Memory Bank 5 (Epson VGA) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_EBC_PB5AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
366#define CONFIG_SYS_EBC_PB5CR VGA_BA | 0x5A000 /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000367
368/* Memory Bank 6 (PCMCIA Slot 2) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_EBC_PB6AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
370#define CONFIG_SYS_EBC_PB6CR PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
stroesea20b27a2004-12-16 18:05:42 +0000371
Matthias Fuchs1c686672008-04-21 14:42:17 +0200372/*
stroesea20b27a2004-12-16 18:05:42 +0000373 * FPGA stuff
374 */
375
376/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_FPGA_CTRL 0x008
378#define CONFIG_SYS_FPGA_CTRL2 0x00a
stroesea20b27a2004-12-16 18:05:42 +0000379
380/* FPGA Control Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_FPGA_CTRL_CF_RESET 0x0001
382#define CONFIG_SYS_FPGA_CTRL_WDI 0x0002
383#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
stroesea20b27a2004-12-16 18:05:42 +0000384
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
386#define CONFIG_SYS_FPGA_MAX_SIZE 80*1024 /* 80kByte is enough for XC2S50 */
stroesea20b27a2004-12-16 18:05:42 +0000387
388/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
390#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
391#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
392#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
393#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroesea20b27a2004-12-16 18:05:42 +0000394
Matthias Fuchs1c686672008-04-21 14:42:17 +0200395/*
stroesea20b27a2004-12-16 18:05:42 +0000396 * LCD Setup
397 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_LCD_BIG_MEM (VGA_BA + 0x200000) /* S1D13806 Mem Base */
399#define CONFIG_SYS_LCD_BIG_REG VGA_BA /* S1D13806 Reg Base */
stroesea20b27a2004-12-16 18:05:42 +0000400
Matthias Fuchs1c686672008-04-21 14:42:17 +0200401#define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */
stroesea20b27a2004-12-16 18:05:42 +0000402
403/* Image information... */
Matthias Fuchs1c686672008-04-21 14:42:17 +0200404#define CONFIG_LCD_USED CONFIG_LCD_BIG
stroesea20b27a2004-12-16 18:05:42 +0000405
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_LCD_MEM CONFIG_SYS_LCD_BIG_MEM
407#define CONFIG_SYS_LCD_REG CONFIG_SYS_LCD_BIG_REG
stroesea20b27a2004-12-16 18:05:42 +0000408
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
stroesea20b27a2004-12-16 18:05:42 +0000410
Matthias Fuchs1c686672008-04-21 14:42:17 +0200411/*
stroesea20b27a2004-12-16 18:05:42 +0000412 * Definitions for initial stack pointer and data area (in data cache)
413 */
414
415/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_TEMP_STACK_OCM 1
stroesea20b27a2004-12-16 18:05:42 +0000417
418/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
420#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
stroesea20b27a2004-12-16 18:05:42 +0000421
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
423#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
424#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved bytes for initial data */
425#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
Matthias Fuchs8e048c42008-04-25 12:01:39 +0200426/* reserve some memory for BOOT limit info */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16)
Matthias Fuchs8e048c42008-04-25 12:01:39 +0200428
429#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 8)
Matthias Fuchs8e048c42008-04-25 12:01:39 +0200431#endif
stroesea20b27a2004-12-16 18:05:42 +0000432
433/*
Matthias Fuchs1c686672008-04-21 14:42:17 +0200434 * PCI OHCI controller
435 */
436#define CONFIG_USB_OHCI_NEW 1
437#define CONFIG_PCI_OHCI 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
439#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
440#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
Matthias Fuchs1c686672008-04-21 14:42:17 +0200441#define CONFIG_USB_STORAGE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
Matthias Fuchs1c686672008-04-21 14:42:17 +0200443
444#endif /* __CONFIG_H */