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wdenk42d1f032003-10-15 23:53:47 +00001/*
Dipen Dudhatbeba93e2011-01-19 12:46:27 +05302 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
Kumar Gala39aaca12009-03-19 02:46:19 -05003 *
wdenk42d1f032003-10-15 23:53:47 +00004 * (C) Copyright 2003 Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +000011 */
12
13#include <common.h>
14#include <ppc_asm.tmpl>
Haiying Wanga52d2f82011-02-11 01:25:30 -060015#include <linux/compiler.h>
wdenk42d1f032003-10-15 23:53:47 +000016#include <asm/processor.h>
Trent Piephoada591d2008-12-03 15:16:37 -080017#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000018
Wolfgang Denkd87080b2006-03-31 18:32:53 +020019DECLARE_GLOBAL_DATA_PTR;
20
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +053021
22#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
23#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
24#endif
wdenk42d1f032003-10-15 23:53:47 +000025/* --------------------------------------------------------------- */
26
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053027void get_sys_info(sys_info_t *sys_info)
wdenk42d1f032003-10-15 23:53:47 +000028{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala800c73c2012-10-08 07:44:06 +000030#ifdef CONFIG_FSL_IFC
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -070031 struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
Kumar Gala800c73c2012-10-08 07:44:06 +000032 u32 ccr;
33#endif
Kumar Gala39aaca12009-03-19 02:46:19 -050034#ifdef CONFIG_FSL_CORENET
35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
Timur Tabifbb9ecf2011-08-05 16:15:24 -050036 unsigned int cpu;
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +053037#ifdef CONFIG_HETROGENOUS_CLUSTERS
38 unsigned int dsp_cpu;
39 uint rcw_tmp1, rcw_tmp2;
40#endif
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +053041#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
42 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
43#endif
York Sun14109c72014-10-27 11:31:33 -070044 __maybe_unused u32 svr;
Kumar Gala39aaca12009-03-19 02:46:19 -050045
46 const u8 core_cplx_PLL[16] = {
47 [ 0] = 0, /* CC1 PPL / 1 */
48 [ 1] = 0, /* CC1 PPL / 2 */
49 [ 2] = 0, /* CC1 PPL / 4 */
50 [ 4] = 1, /* CC2 PPL / 1 */
51 [ 5] = 1, /* CC2 PPL / 2 */
52 [ 6] = 1, /* CC2 PPL / 4 */
53 [ 8] = 2, /* CC3 PPL / 1 */
54 [ 9] = 2, /* CC3 PPL / 2 */
55 [10] = 2, /* CC3 PPL / 4 */
56 [12] = 3, /* CC4 PPL / 1 */
57 [13] = 3, /* CC4 PPL / 2 */
58 [14] = 3, /* CC4 PPL / 4 */
59 };
60
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053061 const u8 core_cplx_pll_div[16] = {
Kumar Gala39aaca12009-03-19 02:46:19 -050062 [ 0] = 1, /* CC1 PPL / 1 */
63 [ 1] = 2, /* CC1 PPL / 2 */
64 [ 2] = 4, /* CC1 PPL / 4 */
65 [ 4] = 1, /* CC2 PPL / 1 */
66 [ 5] = 2, /* CC2 PPL / 2 */
67 [ 6] = 4, /* CC2 PPL / 4 */
68 [ 8] = 1, /* CC3 PPL / 1 */
69 [ 9] = 2, /* CC3 PPL / 2 */
70 [10] = 4, /* CC3 PPL / 4 */
71 [12] = 1, /* CC4 PPL / 1 */
72 [13] = 2, /* CC4 PPL / 2 */
73 [14] = 4, /* CC4 PPL / 4 */
74 };
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +053075 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +080076#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \
77 defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +053078 uint rcw_tmp;
79#endif
80 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
Kumar Gala39aaca12009-03-19 02:46:19 -050081 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080082 uint mem_pll_rat;
Kumar Gala39aaca12009-03-19 02:46:19 -050083
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053084 sys_info->freq_systembus = sysclk;
Priyanka Jainb1359912013-12-17 14:25:52 +053085#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
vijay rai0c12a152014-04-15 11:34:12 +053086 uint ddr_refclk_sel;
87 unsigned int porsr1_sys_clk;
88 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
89 & FSL_DCFG_PORSR1_SYSCLK_MASK;
90 if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
91 sys_info->diff_sysclk = 1;
92 else
93 sys_info->diff_sysclk = 0;
94
Priyanka Jainb1359912013-12-17 14:25:52 +053095 /*
96 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
97 * are driven by separate DDR Refclock or single source
98 * differential clock.
99 */
vijay rai0c12a152014-04-15 11:34:12 +0530100 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
Priyanka Jainb1359912013-12-17 14:25:52 +0530101 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
102 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
103 /*
vijay rai0c12a152014-04-15 11:34:12 +0530104 * For single source clocking, both ddrclock and sysclock
Priyanka Jainb1359912013-12-17 14:25:52 +0530105 * are driven by differential sysclock.
106 */
vijay rai0c12a152014-04-15 11:34:12 +0530107 if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
Priyanka Jainb1359912013-12-17 14:25:52 +0530108 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
vijay rai0c12a152014-04-15 11:34:12 +0530109 else
Priyanka Jainb1359912013-12-17 14:25:52 +0530110#endif
York Sun98ffa192012-10-08 07:44:31 +0000111#ifdef CONFIG_DDR_CLK_FREQ
Priyanka Jainb1359912013-12-17 14:25:52 +0530112 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
York Sun98ffa192012-10-08 07:44:31 +0000113#else
Priyanka Jainb1359912013-12-17 14:25:52 +0530114 sys_info->freq_ddrbus = sysclk;
York Sun98ffa192012-10-08 07:44:31 +0000115#endif
Kumar Gala39aaca12009-03-19 02:46:19 -0500116
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530117 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
York Sunf77329c2012-10-08 07:44:09 +0000118 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
119 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
120 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
York Sunc3678b02014-03-28 15:07:27 -0700121#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
122 if (mem_pll_rat == 0) {
123 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
124 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
125 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
126 }
127#endif
Zang Roy-R61911e88f4212013-11-28 13:23:37 +0800128 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
129 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
130 * it uses 6.
York Sun14109c72014-10-27 11:31:33 -0700131 * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
Zang Roy-R61911e88f4212013-11-28 13:23:37 +0800132 */
Shengzhou Liu5122dfa2014-04-25 16:31:22 +0800133#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
Shengzhou Liu96d59e92015-10-26 13:51:58 +0800134 defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \
135 defined(CONFIG_PPC_T2081)
York Sun14109c72014-10-27 11:31:33 -0700136 svr = get_svr();
137 switch (SVR_SOC_VER(svr)) {
138 case SVR_T4240:
139 case SVR_T4160:
140 case SVR_T4120:
141 case SVR_T4080:
142 if (SVR_MAJ(svr) >= 2)
143 mem_pll_rat *= 2;
144 break;
145 case SVR_T2080:
146 case SVR_T2081:
147 if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
148 mem_pll_rat *= 2;
149 break;
150 default:
151 break;
152 }
Zang Roy-R61911e88f4212013-11-28 13:23:37 +0800153#endif
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800154 if (mem_pll_rat > 2)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530155 sys_info->freq_ddrbus *= mem_pll_rat;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800156 else
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530157 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
Kumar Gala39aaca12009-03-19 02:46:19 -0500158
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530159 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
160 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800161 if (ratio[i] > 4)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530162 freq_c_pll[i] = sysclk * ratio[i];
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800163 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530164 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800165 }
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530166
York Sun9a653a92012-10-08 07:44:11 +0000167#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
168 /*
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530169 * As per CHASSIS2 architeture total 12 clusters are posible and
York Sun9a653a92012-10-08 07:44:11 +0000170 * Each cluster has up to 4 cores, sharing the same PLL selection.
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530171 * The cluster clock assignment is SoC defined.
172 *
173 * Total 4 clock groups are possible with 3 PLLs each.
174 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
175 * clock group B has 3, 4, 6 and so on.
176 *
177 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
178 * depends upon the SoC architeture. Same applies to other
179 * clock groups and clusters.
180 *
York Sun9a653a92012-10-08 07:44:11 +0000181 */
182 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
York Sunf6981432013-03-25 07:40:07 +0000183 int cluster = fsl_qoriq_core_to_cluster(cpu);
184 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
York Sun9a653a92012-10-08 07:44:11 +0000185 & 0xf;
186 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530187 cplx_pll += cc_group[cluster] - 1;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530188 sys_info->freq_processor[cpu] =
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530189 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
York Sun9a653a92012-10-08 07:44:11 +0000190 }
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530191
192#ifdef CONFIG_HETROGENOUS_CLUSTERS
193 for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
194 int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
195 u32 c_pll_sel = (in_be32
196 (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
197 & 0xf;
198 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
199 cplx_pll += cc_group[dsp_cluster] - 1;
200 sys_info->freq_processor_dsp[dsp_cpu] =
201 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
202 }
203#endif
204
Prabhakar Kushwahab33bd8c2014-04-21 10:47:41 +0530205#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
206 defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
Sandeep Singh0cb33252013-03-25 07:33:09 +0000207#define FM1_CLK_SEL 0xe0000000
208#define FM1_CLK_SHIFT 29
Shengzhou Liuf6050792014-11-24 17:11:54 +0800209#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
210#define FM1_CLK_SEL 0x00000007
211#define FM1_CLK_SHIFT 0
Sandeep Singh0cb33252013-03-25 07:33:09 +0000212#else
York Sun9a653a92012-10-08 07:44:11 +0000213#define PME_CLK_SEL 0xe0000000
214#define PME_CLK_SHIFT 29
215#define FM1_CLK_SEL 0x1c000000
216#define FM1_CLK_SHIFT 26
Sandeep Singh0cb33252013-03-25 07:33:09 +0000217#endif
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530218#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
Shengzhou Liuf6050792014-11-24 17:11:54 +0800219#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
220 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
221#else
York Sun9a653a92012-10-08 07:44:11 +0000222 rcw_tmp = in_be32(&gur->rcwsr[7]);
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530223#endif
Shengzhou Liuf6050792014-11-24 17:11:54 +0800224#endif
York Sun9a653a92012-10-08 07:44:11 +0000225
226#ifdef CONFIG_SYS_DPAA_PME
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530227#ifndef CONFIG_PME_PLAT_CLK_DIV
York Sun9a653a92012-10-08 07:44:11 +0000228 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
229 case 1:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530230 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
York Sun9a653a92012-10-08 07:44:11 +0000231 break;
232 case 2:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530233 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000234 break;
235 case 3:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530236 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000237 break;
238 case 4:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530239 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
York Sun9a653a92012-10-08 07:44:11 +0000240 break;
241 case 6:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530242 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000243 break;
244 case 7:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530245 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000246 break;
247 default:
248 printf("Error: Unknown PME clock select!\n");
249 case 0:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530250 sys_info->freq_pme = sys_info->freq_systembus / 2;
York Sun9a653a92012-10-08 07:44:11 +0000251 break;
252
253 }
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530254#else
255 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
256
257#endif
York Sun9a653a92012-10-08 07:44:11 +0000258#endif
259
Haiying Wang990e1a82012-10-11 07:13:39 +0000260#ifdef CONFIG_SYS_DPAA_QBMAN
Shengzhou Liuf6050792014-11-24 17:11:54 +0800261#ifndef CONFIG_QBMAN_CLK_DIV
262#define CONFIG_QBMAN_CLK_DIV 2
263#endif
264 sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
Haiying Wang990e1a82012-10-11 07:13:39 +0000265#endif
266
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530267#if defined(CONFIG_SYS_MAPLE)
268#define CPRI_CLK_SEL 0x1C000000
269#define CPRI_CLK_SHIFT 26
270#define CPRI_ALT_CLK_SEL 0x00007000
271#define CPRI_ALT_CLK_SHIFT 12
272
273 rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/
274 rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/
275 /* For MAPLE and CPRI frequency */
276 switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
277 case 1:
278 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
279 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
280 break;
281 case 2:
282 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
283 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
284 break;
285 case 3:
286 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
287 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
288 break;
289 case 4:
290 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
291 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
292 break;
293 case 5:
294 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
295 >> CPRI_ALT_CLK_SHIFT) == 6) {
296 sys_info->freq_maple =
297 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
298 sys_info->freq_cpri =
299 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
300 }
301 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
302 >> CPRI_ALT_CLK_SHIFT) == 7) {
303 sys_info->freq_maple =
304 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
305 sys_info->freq_cpri =
306 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
307 }
308 break;
309 case 6:
310 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
311 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
312 break;
313 case 7:
314 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
315 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
316 break;
317 default:
318 printf("Error: Unknown MAPLE/CPRI clock select!\n");
319 }
320
321 /* For MAPLE ULB and eTVPE frequencies */
322#define ULB_CLK_SEL 0x00000038
323#define ULB_CLK_SHIFT 3
324#define ETVPE_CLK_SEL 0x00000007
325#define ETVPE_CLK_SHIFT 0
326
327 switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
328 case 1:
329 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
330 break;
331 case 2:
332 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
333 break;
334 case 3:
335 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
336 break;
337 case 4:
338 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
339 break;
340 case 5:
341 sys_info->freq_maple_ulb = sys_info->freq_systembus;
342 break;
343 case 6:
344 sys_info->freq_maple_ulb =
345 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
346 break;
347 case 7:
348 sys_info->freq_maple_ulb =
349 freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
350 break;
351 default:
352 printf("Error: Unknown MAPLE ULB clock select!\n");
353 }
354
355 switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
356 case 1:
357 sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
358 break;
359 case 2:
360 sys_info->freq_maple_etvpe =
361 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
362 break;
363 case 3:
364 sys_info->freq_maple_etvpe =
365 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
366 break;
367 case 4:
368 sys_info->freq_maple_etvpe =
369 freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
370 break;
371 case 5:
372 sys_info->freq_maple_etvpe = sys_info->freq_systembus;
373 break;
374 case 6:
375 sys_info->freq_maple_etvpe =
376 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
377 break;
378 case 7:
379 sys_info->freq_maple_etvpe =
380 freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
381 break;
382 default:
383 printf("Error: Unknown MAPLE eTVPE clock select!\n");
384 }
385
386#endif
387
York Sun9a653a92012-10-08 07:44:11 +0000388#ifdef CONFIG_SYS_DPAA_FMAN
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530389#ifndef CONFIG_FM_PLAT_CLK_DIV
York Sun9a653a92012-10-08 07:44:11 +0000390 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
391 case 1:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530392 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
York Sun9a653a92012-10-08 07:44:11 +0000393 break;
394 case 2:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530395 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000396 break;
397 case 3:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530398 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000399 break;
400 case 4:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530401 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
York Sun9a653a92012-10-08 07:44:11 +0000402 break;
Sandeep Singh0cb33252013-03-25 07:33:09 +0000403 case 5:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530404 sys_info->freq_fman[0] = sys_info->freq_systembus;
Sandeep Singh0cb33252013-03-25 07:33:09 +0000405 break;
York Sun9a653a92012-10-08 07:44:11 +0000406 case 6:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530407 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000408 break;
409 case 7:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530410 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000411 break;
412 default:
413 printf("Error: Unknown FMan1 clock select!\n");
414 case 0:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530415 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
York Sun9a653a92012-10-08 07:44:11 +0000416 break;
417 }
418#if (CONFIG_SYS_NUM_FMAN) == 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530419#ifdef CONFIG_SYS_FM2_CLK
York Sun9a653a92012-10-08 07:44:11 +0000420#define FM2_CLK_SEL 0x00000038
421#define FM2_CLK_SHIFT 3
422 rcw_tmp = in_be32(&gur->rcwsr[15]);
423 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
424 case 1:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530425 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
York Sun9a653a92012-10-08 07:44:11 +0000426 break;
427 case 2:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530428 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000429 break;
430 case 3:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530431 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000432 break;
433 case 4:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530434 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
York Sun9a653a92012-10-08 07:44:11 +0000435 break;
Shaohui Xiec1015c62013-11-28 13:52:51 +0800436 case 5:
437 sys_info->freq_fman[1] = sys_info->freq_systembus;
438 break;
York Sun9a653a92012-10-08 07:44:11 +0000439 case 6:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530440 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000441 break;
442 case 7:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530443 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000444 break;
445 default:
446 printf("Error: Unknown FMan2 clock select!\n");
447 case 0:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530448 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
York Sun9a653a92012-10-08 07:44:11 +0000449 break;
450 }
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530451#endif
York Sun9a653a92012-10-08 07:44:11 +0000452#endif /* CONFIG_SYS_NUM_FMAN == 2 */
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530453#else
454 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
455#endif
456#endif
York Sun9a653a92012-10-08 07:44:11 +0000457
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800458#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
459#if defined(CONFIG_PPC_T2080)
460#define ESDHC_CLK_SEL 0x00000007
461#define ESDHC_CLK_SHIFT 0
462#define ESDHC_CLK_RCWSR 15
463#else /* Support T1040 T1024 by now */
464#define ESDHC_CLK_SEL 0xe0000000
465#define ESDHC_CLK_SHIFT 29
466#define ESDHC_CLK_RCWSR 7
467#endif
468 rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]);
469 switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) {
470 case 1:
471 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK];
472 break;
473 case 2:
474 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2;
475 break;
476 case 3:
477 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3;
478 break;
479#if defined(CONFIG_SYS_SDHC_CLK_2_PLL)
480 case 4:
481 sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
482 break;
483#if defined(CONFIG_PPC_T2080)
484 case 5:
485 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
486 break;
487#endif
488 case 6:
489 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2;
490 break;
491 case 7:
492 sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3;
493 break;
494#endif
495 default:
496 sys_info->freq_sdhc = 0;
497 printf("Error: Unknown SDHC peripheral clock select!\n");
498 }
499#endif
York Sun9a653a92012-10-08 07:44:11 +0000500#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
501
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500502 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
York Sunf6981432013-03-25 07:40:07 +0000503 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
504 & 0xf;
Kumar Gala39aaca12009-03-19 02:46:19 -0500505 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
506
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530507 sys_info->freq_processor[cpu] =
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530508 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
Kumar Gala39aaca12009-03-19 02:46:19 -0500509 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500510#define PME_CLK_SEL 0x80000000
511#define FM1_CLK_SEL 0x40000000
512#define FM2_CLK_SEL 0x20000000
Kumar Galab5c87532011-02-16 02:03:29 -0600513#define HWA_ASYNC_DIV 0x04000000
514#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
515#define HWA_CC_PLL 1
Timur Tabi49054432012-10-05 11:09:19 +0000516#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
517#define HWA_CC_PLL 2
Kumar Galab5c87532011-02-16 02:03:29 -0600518#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
Wolfgang Denkcd6881b2011-05-19 22:21:41 +0200519#define HWA_CC_PLL 2
Kumar Galab5c87532011-02-16 02:03:29 -0600520#else
521#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
522#endif
Kumar Gala39aaca12009-03-19 02:46:19 -0500523 rcw_tmp = in_be32(&gur->rcwsr[7]);
524
525#ifdef CONFIG_SYS_DPAA_PME
Kumar Galab5c87532011-02-16 02:03:29 -0600526 if (rcw_tmp & PME_CLK_SEL) {
527 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530528 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Galab5c87532011-02-16 02:03:29 -0600529 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530530 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600531 } else {
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530532 sys_info->freq_pme = sys_info->freq_systembus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600533 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500534#endif
535
536#ifdef CONFIG_SYS_DPAA_FMAN
Kumar Galab5c87532011-02-16 02:03:29 -0600537 if (rcw_tmp & FM1_CLK_SEL) {
538 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530539 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Galab5c87532011-02-16 02:03:29 -0600540 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530541 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600542 } else {
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530543 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600544 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500545#if (CONFIG_SYS_NUM_FMAN) == 2
Kumar Galab5c87532011-02-16 02:03:29 -0600546 if (rcw_tmp & FM2_CLK_SEL) {
547 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530548 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Galab5c87532011-02-16 02:03:29 -0600549 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530550 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600551 } else {
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530552 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600553 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500554#endif
555#endif
556
Shaohui Xie3e83fc92013-03-25 07:33:25 +0000557#ifdef CONFIG_SYS_DPAA_QBMAN
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530558 sys_info->freq_qman = sys_info->freq_systembus / 2;
Shaohui Xie3e83fc92013-03-25 07:33:25 +0000559#endif
560
York Sun9a653a92012-10-08 07:44:11 +0000561#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
562
Zhao Qiang2a44efe2014-03-21 16:21:45 +0800563#ifdef CONFIG_U_QE
564 sys_info->freq_qe = sys_info->freq_systembus / 2;
565#endif
566
York Sun9a653a92012-10-08 07:44:11 +0000567#else /* CONFIG_FSL_CORENET */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530568 uint plat_ratio, e500_ratio, half_freq_systembus;
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500569 int i;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400570#ifdef CONFIG_QE
Haiying Wanga52d2f82011-02-11 01:25:30 -0600571 __maybe_unused u32 qe_ratio;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400572#endif
wdenk42d1f032003-10-15 23:53:47 +0000573
574 plat_ratio = (gur->porpllsr) & 0x0000003e;
575 plat_ratio >>= 1;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530576 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500577
578 /* Divide before multiply to avoid integer
579 * overflow for processor speeds above 2GHz */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530580 half_freq_systembus = sys_info->freq_systembus/2;
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530581 for (i = 0; i < cpu_numcores(); i++) {
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500582 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530583 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500584 }
James Yanga3e77fa2008-02-08 18:05:08 -0600585
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530586 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
587 sys_info->freq_ddrbus = sys_info->freq_systembus;
Kumar Galad4357932007-12-07 04:59:26 -0600588
589#ifdef CONFIG_DDR_CLK_FREQ
590 {
Jason Jinc0391112008-09-27 14:40:57 +0800591 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
592 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
Kumar Galad4357932007-12-07 04:59:26 -0600593 if (ddr_ratio != 0x7)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530594 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
Kumar Galad4357932007-12-07 04:59:26 -0600595 }
596#endif
Trent Piephoada591d2008-12-03 15:16:37 -0800597
Haiying Wangb3d7f202009-05-20 12:30:29 -0400598#ifdef CONFIG_QE
York Sunbe7bebe2012-08-10 11:07:26 +0000599#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530600 sys_info->freq_qe = sys_info->freq_systembus;
Haiying Wanga52d2f82011-02-11 01:25:30 -0600601#else
Haiying Wangb3d7f202009-05-20 12:30:29 -0400602 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
603 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530604 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400605#endif
Haiying Wanga52d2f82011-02-11 01:25:30 -0600606#endif
Haiying Wangb3d7f202009-05-20 12:30:29 -0400607
Haiying Wang24995d82011-01-20 22:26:31 +0000608#ifdef CONFIG_SYS_DPAA_FMAN
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530609 sys_info->freq_fman[0] = sys_info->freq_systembus;
Haiying Wang24995d82011-01-20 22:26:31 +0000610#endif
611
612#endif /* CONFIG_FSL_CORENET */
613
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530614#if defined(CONFIG_FSL_LBC)
York Sun9a653a92012-10-08 07:44:11 +0000615 uint lcrr_div;
Trent Piephoada591d2008-12-03 15:16:37 -0800616#if defined(CONFIG_SYS_LBC_LCRR)
617 /* We will program LCRR to this value later */
618 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
619#else
Becky Brucef51cdaf2010-06-17 11:37:20 -0500620 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
Trent Piephoada591d2008-12-03 15:16:37 -0800621#endif
622 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
Dave Liu0fd2fa62009-11-17 20:49:05 +0800623#if defined(CONFIG_FSL_CORENET)
624 /* If this is corenet based SoC, bit-representation
625 * for four times the clock divider values.
626 */
627 lcrr_div *= 4;
628#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
Trent Piephoada591d2008-12-03 15:16:37 -0800629 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
630 /*
631 * Yes, the entire PQ38 family use the same
632 * bit-representation for twice the clock divider values.
633 */
634 lcrr_div *= 2;
635#endif
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530636 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
Trent Piephoada591d2008-12-03 15:16:37 -0800637 } else {
638 /* In case anyone cares what the unknown value is */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530639 sys_info->freq_localbus = lcrr_div;
Trent Piephoada591d2008-12-03 15:16:37 -0800640 }
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530641#endif
Kumar Gala800c73c2012-10-08 07:44:06 +0000642
643#if defined(CONFIG_FSL_IFC)
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -0700644 ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
Kumar Gala800c73c2012-10-08 07:44:06 +0000645 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
646
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530647 sys_info->freq_localbus = sys_info->freq_systembus / ccr;
Kumar Gala800c73c2012-10-08 07:44:06 +0000648#endif
wdenk42d1f032003-10-15 23:53:47 +0000649}
650
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500651
wdenk42d1f032003-10-15 23:53:47 +0000652int get_clocks (void)
653{
wdenk42d1f032003-10-15 23:53:47 +0000654 sys_info_t sys_info;
Timur Tabi88353a92008-04-04 11:15:58 -0500655#ifdef CONFIG_MPC8544
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200656 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
Timur Tabi88353a92008-04-04 11:15:58 -0500657#endif
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500658#if defined(CONFIG_CPM2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200659 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
wdenk42d1f032003-10-15 23:53:47 +0000660 uint sccr, dfbrg;
661
662 /* set VCO = 4 * BRG */
Kumar Galaaafeefb2007-11-28 00:36:33 -0600663 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
664 sccr = cpm->im_cpm_intctl.sccr;
wdenk42d1f032003-10-15 23:53:47 +0000665 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
666#endif
667 get_sys_info (&sys_info);
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530668 gd->cpu_clk = sys_info.freq_processor[0];
669 gd->bus_clk = sys_info.freq_systembus;
670 gd->mem_clk = sys_info.freq_ddrbus;
671 gd->arch.lbc_clk = sys_info.freq_localbus;
Timur Tabi88353a92008-04-04 11:15:58 -0500672
Haiying Wangb3d7f202009-05-20 12:30:29 -0400673#ifdef CONFIG_QE
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530674 gd->arch.qe_clk = sys_info.freq_qe;
Simon Glass45bae2e2012-12-13 20:48:50 +0000675 gd->arch.brg_clk = gd->arch.qe_clk / 2;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400676#endif
Timur Tabi88353a92008-04-04 11:15:58 -0500677 /*
678 * The base clock for I2C depends on the actual SOC. Unfortunately,
679 * there is no pattern that can be used to determine the frequency, so
680 * the only choice is to look up the actual SOC number and use the value
681 * for that SOC. This information is taken from application note
682 * AN2919.
683 */
684#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
Tang Yuantianf62b1232013-09-06 10:45:40 +0800685 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
686 defined(CONFIG_P1022)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530687 gd->arch.i2c1_clk = sys_info.freq_systembus;
Timur Tabi88353a92008-04-04 11:15:58 -0500688#elif defined(CONFIG_MPC8544)
689 /*
690 * On the 8544, the I2C clock is the same as the SEC clock. This can be
691 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
692 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
693 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
694 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
695 */
696 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530697 gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
Kumar Gala42653b82008-10-16 21:58:49 -0500698 else
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530699 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
Timur Tabi88353a92008-04-04 11:15:58 -0500700#else
701 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530702 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
Timur Tabi88353a92008-04-04 11:15:58 -0500703#endif
Simon Glass609e6ec2012-12-13 20:48:49 +0000704 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
Timur Tabi943afa22008-01-09 14:35:26 -0600705
Dipen Dudhat6b9ea082009-09-01 17:27:00 +0530706#if defined(CONFIG_FSL_ESDHC)
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800707#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
708 gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
709#else
Priyanka Jain7d640e92011-02-08 15:45:25 +0530710#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
711 defined(CONFIG_P1014)
Simon Glasse9adeca2012-12-13 20:49:05 +0000712 gd->arch.sdhc_clk = gd->bus_clk;
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400713#else
Simon Glasse9adeca2012-12-13 20:49:05 +0000714 gd->arch.sdhc_clk = gd->bus_clk / 2;
Kumar Galaef50d6c2008-08-12 11:14:19 -0500715#endif
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800716#endif
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400717#endif /* defined(CONFIG_FSL_ESDHC) */
Kumar Galaef50d6c2008-08-12 11:14:19 -0500718
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500719#if defined(CONFIG_CPM2)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530720 gd->arch.vco_out = 2*sys_info.freq_systembus;
Simon Glass748cd052012-12-13 20:48:46 +0000721 gd->arch.cpm_clk = gd->arch.vco_out / 2;
722 gd->arch.scc_clk = gd->arch.vco_out / 4;
723 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
wdenk42d1f032003-10-15 23:53:47 +0000724#endif
725
726 if(gd->cpu_clk != 0) return (0);
727 else return (1);
728}
729
730
731/********************************************
732 * get_bus_freq
733 * return system bus freq in Hz
734 *********************************************/
735ulong get_bus_freq (ulong dummy)
736{
James Yanga3e77fa2008-02-08 18:05:08 -0600737 return gd->bus_clk;
wdenk42d1f032003-10-15 23:53:47 +0000738}
Kumar Galad4357932007-12-07 04:59:26 -0600739
740/********************************************
741 * get_ddr_freq
742 * return ddr bus freq in Hz
743 *********************************************/
744ulong get_ddr_freq (ulong dummy)
745{
James Yanga3e77fa2008-02-08 18:05:08 -0600746 return gd->mem_clk;
Kumar Galad4357932007-12-07 04:59:26 -0600747}