| Dirk Eibach | 2da0fc0 | 2011-01-21 09:31:21 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef __GDSYS_FPGA_H |
| 25 | #define __GDSYS_FPGA_H |
| 26 | |
| 27 | enum { |
| 28 | FPGA_STATE_DONE_FAILED = 1 << 0, |
| 29 | FPGA_STATE_REFLECTION_FAILED = 1 << 1, |
| 30 | }; |
| 31 | |
| 32 | int get_fpga_state(unsigned dev); |
| 33 | void print_fpga_state(unsigned dev); |
| 34 | |
| 35 | typedef struct ihs_gpio { |
| 36 | u16 read; |
| 37 | u16 clear; |
| 38 | u16 set; |
| 39 | } ihs_gpio_t; |
| 40 | |
| 41 | typedef struct ihs_i2c { |
| 42 | u16 write_mailbox; |
| 43 | u16 write_mailbox_ext; |
| 44 | u16 read_mailbox; |
| 45 | u16 read_mailbox_ext; |
| 46 | } ihs_i2c_t; |
| 47 | |
| 48 | typedef struct ihs_osd { |
| 49 | u16 version; |
| 50 | u16 features; |
| 51 | u16 control; |
| 52 | u16 xy_size; |
| 53 | } ihs_osd_t; |
| 54 | |
| 55 | #ifdef CONFIG_IO |
| 56 | typedef struct ihs_fpga { |
| 57 | u16 reflection_low; /* 0x0000 */ |
| 58 | u16 versions; /* 0x0002 */ |
| 59 | u16 fpga_features; /* 0x0004 */ |
| 60 | u16 fpga_version; /* 0x0006 */ |
| 61 | u16 reserved_0[5]; /* 0x0008 */ |
| 62 | u16 quad_serdes_reset; /* 0x0012 */ |
| 63 | u16 reserved_1[8181]; /* 0x0014 */ |
| 64 | u16 reflection_high; /* 0x3ffe */ |
| 65 | } ihs_fpga_t; |
| 66 | #endif |
| 67 | |
| 68 | #ifdef CONFIG_IOCON |
| 69 | typedef struct ihs_fpga { |
| 70 | u16 reflection_low; /* 0x0000 */ |
| 71 | u16 versions; /* 0x0002 */ |
| 72 | u16 fpga_version; /* 0x0004 */ |
| 73 | u16 fpga_features; /* 0x0006 */ |
| 74 | u16 reserved_0[6]; /* 0x0008 */ |
| 75 | ihs_gpio_t gpio; /* 0x0014 */ |
| 76 | u16 mpc3w_control; /* 0x001a */ |
| 77 | u16 reserved_1[19]; /* 0x001c */ |
| 78 | u16 videocontrol; /* 0x0042 */ |
| 79 | u16 reserved_2[93]; /* 0x0044 */ |
| 80 | u16 reflection_high; /* 0x00fe */ |
| 81 | ihs_osd_t osd; /* 0x0100 */ |
| 82 | u16 reserved_3[892]; /* 0x0108 */ |
| 83 | u16 videomem; /* 0x0800 */ |
| 84 | } ihs_fpga_t; |
| 85 | #endif |
| 86 | |
| 87 | #ifdef CONFIG_DLVISION_10G |
| 88 | typedef struct ihs_fpga { |
| 89 | u16 reflection_low; /* 0x0000 */ |
| 90 | u16 versions; /* 0x0002 */ |
| 91 | u16 fpga_version; /* 0x0004 */ |
| 92 | u16 fpga_features; /* 0x0006 */ |
| 93 | u16 reserved_0[10]; /* 0x0008 */ |
| 94 | u16 extended_interrupt; /* 0x001c */ |
| 95 | u16 reserved_1[9]; /* 0x001e */ |
| 96 | ihs_i2c_t i2c; /* 0x0030 */ |
| 97 | u16 reserved_2[35]; /* 0x0038 */ |
| 98 | u16 reflection_high; /* 0x007e */ |
| 99 | u16 reserved_3[15]; /* 0x0080 */ |
| 100 | u16 videocontrol; /* 0x009e */ |
| 101 | u16 reserved_4[176]; /* 0x00a0 */ |
| 102 | ihs_osd_t osd; /* 0x0200 */ |
| 103 | u16 reserved_5[764]; /* 0x0208 */ |
| 104 | u16 videomem; /* 0x0800 */ |
| 105 | } ihs_fpga_t; |
| 106 | #endif |
| 107 | |
| 108 | #endif |