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Marek Vasut31650d62011-11-08 23:18:15 +00001/*
2 * Freescale i.MX28 APBH DMA driver
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25#include <linux/list.h>
26
27#include <common.h>
28#include <malloc.h>
29#include <asm/errno.h>
30#include <asm/io.h>
31#include <asm/arch/clock.h>
32#include <asm/arch/imx-regs.h>
33#include <asm/arch/sys_proto.h>
34#include <asm/arch/dma.h>
35
36static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
37
38/*
39 * Test is the DMA channel is valid channel
40 */
41int mxs_dma_validate_chan(int channel)
42{
43 struct mxs_dma_chan *pchan;
44
45 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
46 return -EINVAL;
47
48 pchan = mxs_dma_channels + channel;
49 if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
50 return -EINVAL;
51
52 return 0;
53}
54
55/*
Marek Vasutaa72e432011-11-23 10:59:13 +000056 * Return the address of the command within a descriptor.
57 */
58static unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
59{
60 return desc->address + offsetof(struct mxs_dma_desc, cmd);
61}
62
63/*
64 * Read a DMA channel's hardware semaphore.
65 *
66 * As used by the MXS platform's DMA software, the DMA channel's hardware
67 * semaphore reflects the number of DMA commands the hardware will process, but
68 * has not yet finished. This is a volatile value read directly from hardware,
69 * so it must be be viewed as immediately stale.
70 *
71 * If the channel is not marked busy, or has finished processing all its
72 * commands, this value should be zero.
73 *
74 * See mxs_dma_append() for details on how DMA command blocks must be configured
75 * to maintain the expected behavior of the semaphore's value.
76 */
77static int mxs_dma_read_semaphore(int channel)
78{
79 struct mx28_apbh_regs *apbh_regs =
80 (struct mx28_apbh_regs *)MXS_APBH_BASE;
81 uint32_t tmp;
82 int ret;
83
84 ret = mxs_dma_validate_chan(channel);
85 if (ret)
86 return ret;
87
88 tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema);
89
90 tmp &= APBH_CHn_SEMA_PHORE_MASK;
91 tmp >>= APBH_CHn_SEMA_PHORE_OFFSET;
92
93 return tmp;
94}
95
Marek Vasutc3dfe702012-03-15 18:33:18 +000096#ifndef CONFIG_SYS_DCACHE_OFF
97void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
98{
99 uint32_t addr;
100 uint32_t size;
101
102 addr = (uint32_t)desc;
103 size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT);
104
105 flush_dcache_range(addr, addr + size);
106}
107#else
108inline void mxs_dma_flush_desc(struct mxs_dma_desc *desc) {}
109#endif
110
Marek Vasutaa72e432011-11-23 10:59:13 +0000111/*
Marek Vasut31650d62011-11-08 23:18:15 +0000112 * Enable a DMA channel.
113 *
114 * If the given channel has any DMA descriptors on its active list, this
115 * function causes the DMA hardware to begin processing them.
116 *
117 * This function marks the DMA channel as "busy," whether or not there are any
118 * descriptors to process.
119 */
Marek Vasutaa72e432011-11-23 10:59:13 +0000120static int mxs_dma_enable(int channel)
Marek Vasut31650d62011-11-08 23:18:15 +0000121{
122 struct mx28_apbh_regs *apbh_regs =
123 (struct mx28_apbh_regs *)MXS_APBH_BASE;
124 unsigned int sem;
125 struct mxs_dma_chan *pchan;
126 struct mxs_dma_desc *pdesc;
127 int ret;
128
129 ret = mxs_dma_validate_chan(channel);
130 if (ret)
131 return ret;
132
133 pchan = mxs_dma_channels + channel;
134
135 if (pchan->pending_num == 0) {
136 pchan->flags |= MXS_DMA_FLAGS_BUSY;
137 return 0;
138 }
139
140 pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
141 if (pdesc == NULL)
142 return -EFAULT;
143
144 if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
145 if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))
146 return 0;
147
148 sem = mxs_dma_read_semaphore(channel);
149 if (sem == 0)
150 return 0;
151
152 if (sem == 1) {
153 pdesc = list_entry(pdesc->node.next,
154 struct mxs_dma_desc, node);
155 writel(mxs_dma_cmd_address(pdesc),
156 &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
157 }
158 writel(pchan->pending_num,
159 &apbh_regs->ch[channel].hw_apbh_ch_sema);
160 pchan->active_num += pchan->pending_num;
161 pchan->pending_num = 0;
162 } else {
163 pchan->active_num += pchan->pending_num;
164 pchan->pending_num = 0;
165 writel(mxs_dma_cmd_address(pdesc),
166 &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
167 writel(pchan->active_num,
168 &apbh_regs->ch[channel].hw_apbh_ch_sema);
169 writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
170 &apbh_regs->hw_apbh_ctrl0_clr);
171 }
172
173 pchan->flags |= MXS_DMA_FLAGS_BUSY;
174 return 0;
175}
176
177/*
178 * Disable a DMA channel.
179 *
180 * This function shuts down a DMA channel and marks it as "not busy." Any
181 * descriptors on the active list are immediately moved to the head of the
182 * "done" list, whether or not they have actually been processed by the
183 * hardware. The "ready" flags of these descriptors are NOT cleared, so they
184 * still appear to be active.
185 *
186 * This function immediately shuts down a DMA channel's hardware, aborting any
187 * I/O that may be in progress, potentially leaving I/O hardware in an undefined
188 * state. It is unwise to call this function if there is ANY chance the hardware
189 * is still processing a command.
190 */
Marek Vasutaa72e432011-11-23 10:59:13 +0000191static int mxs_dma_disable(int channel)
Marek Vasut31650d62011-11-08 23:18:15 +0000192{
193 struct mxs_dma_chan *pchan;
194 struct mx28_apbh_regs *apbh_regs =
195 (struct mx28_apbh_regs *)MXS_APBH_BASE;
196 int ret;
197
198 ret = mxs_dma_validate_chan(channel);
199 if (ret)
200 return ret;
201
202 pchan = mxs_dma_channels + channel;
203
204 if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))
205 return -EINVAL;
206
207 writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
208 &apbh_regs->hw_apbh_ctrl0_set);
209
210 pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
211 pchan->active_num = 0;
212 pchan->pending_num = 0;
213 list_splice_init(&pchan->active, &pchan->done);
214
215 return 0;
216}
217
218/*
219 * Resets the DMA channel hardware.
220 */
Marek Vasutaa72e432011-11-23 10:59:13 +0000221static int mxs_dma_reset(int channel)
Marek Vasut31650d62011-11-08 23:18:15 +0000222{
223 struct mx28_apbh_regs *apbh_regs =
224 (struct mx28_apbh_regs *)MXS_APBH_BASE;
225 int ret;
226
227 ret = mxs_dma_validate_chan(channel);
228 if (ret)
229 return ret;
230
231 writel(1 << (channel + APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET),
232 &apbh_regs->hw_apbh_channel_ctrl_set);
233
234 return 0;
235}
236
237/*
Marek Vasut31650d62011-11-08 23:18:15 +0000238 * Enable or disable DMA interrupt.
239 *
240 * This function enables the given DMA channel to interrupt the CPU.
241 */
Marek Vasutaa72e432011-11-23 10:59:13 +0000242static int mxs_dma_enable_irq(int channel, int enable)
Marek Vasut31650d62011-11-08 23:18:15 +0000243{
244 struct mx28_apbh_regs *apbh_regs =
245 (struct mx28_apbh_regs *)MXS_APBH_BASE;
246 int ret;
247
248 ret = mxs_dma_validate_chan(channel);
249 if (ret)
250 return ret;
251
252 if (enable)
253 writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
254 &apbh_regs->hw_apbh_ctrl1_set);
255 else
256 writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
257 &apbh_regs->hw_apbh_ctrl1_clr);
258
259 return 0;
260}
261
262/*
Marek Vasut31650d62011-11-08 23:18:15 +0000263 * Clear DMA interrupt.
264 *
265 * The software that is using the DMA channel must register to receive its
266 * interrupts and, when they arrive, must call this function to clear them.
267 */
Marek Vasutaa72e432011-11-23 10:59:13 +0000268static int mxs_dma_ack_irq(int channel)
Marek Vasut31650d62011-11-08 23:18:15 +0000269{
270 struct mx28_apbh_regs *apbh_regs =
271 (struct mx28_apbh_regs *)MXS_APBH_BASE;
272 int ret;
273
274 ret = mxs_dma_validate_chan(channel);
275 if (ret)
276 return ret;
277
278 writel(1 << channel, &apbh_regs->hw_apbh_ctrl1_clr);
279 writel(1 << channel, &apbh_regs->hw_apbh_ctrl2_clr);
280
281 return 0;
282}
283
284/*
285 * Request to reserve a DMA channel
286 */
Marek Vasutaa72e432011-11-23 10:59:13 +0000287static int mxs_dma_request(int channel)
Marek Vasut31650d62011-11-08 23:18:15 +0000288{
289 struct mxs_dma_chan *pchan;
290
291 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
292 return -EINVAL;
293
294 pchan = mxs_dma_channels + channel;
295 if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID)
296 return -ENODEV;
297
298 if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED)
299 return -EBUSY;
300
301 pchan->flags |= MXS_DMA_FLAGS_ALLOCATED;
302 pchan->active_num = 0;
303 pchan->pending_num = 0;
304
305 INIT_LIST_HEAD(&pchan->active);
306 INIT_LIST_HEAD(&pchan->done);
307
308 return 0;
309}
310
311/*
312 * Release a DMA channel.
313 *
314 * This function releases a DMA channel from its current owner.
315 *
316 * The channel will NOT be released if it's marked "busy" (see
317 * mxs_dma_enable()).
318 */
Marek Vasut96666a32012-04-08 17:34:46 +0000319int mxs_dma_release(int channel)
Marek Vasut31650d62011-11-08 23:18:15 +0000320{
321 struct mxs_dma_chan *pchan;
322 int ret;
323
324 ret = mxs_dma_validate_chan(channel);
325 if (ret)
326 return ret;
327
328 pchan = mxs_dma_channels + channel;
329
330 if (pchan->flags & MXS_DMA_FLAGS_BUSY)
331 return -EBUSY;
332
333 pchan->dev = 0;
334 pchan->active_num = 0;
335 pchan->pending_num = 0;
336 pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED;
337
338 return 0;
339}
340
341/*
342 * Allocate DMA descriptor
343 */
344struct mxs_dma_desc *mxs_dma_desc_alloc(void)
345{
346 struct mxs_dma_desc *pdesc;
Marek Vasutc3dfe702012-03-15 18:33:18 +0000347 uint32_t size;
Marek Vasut31650d62011-11-08 23:18:15 +0000348
Marek Vasutc3dfe702012-03-15 18:33:18 +0000349 size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT);
350 pdesc = memalign(MXS_DMA_ALIGNMENT, size);
Marek Vasut31650d62011-11-08 23:18:15 +0000351
352 if (pdesc == NULL)
353 return NULL;
354
355 memset(pdesc, 0, sizeof(*pdesc));
356 pdesc->address = (dma_addr_t)pdesc;
357
358 return pdesc;
359};
360
361/*
362 * Free DMA descriptor
363 */
364void mxs_dma_desc_free(struct mxs_dma_desc *pdesc)
365{
366 if (pdesc == NULL)
367 return;
368
369 free(pdesc);
370}
371
372/*
Marek Vasut31650d62011-11-08 23:18:15 +0000373 * Add a DMA descriptor to a channel.
374 *
375 * If the descriptor list for this channel is not empty, this function sets the
376 * CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so
377 * it will chain to the new descriptor's command.
378 *
379 * Then, this function marks the new descriptor as "ready," adds it to the end
380 * of the active descriptor list, and increments the count of pending
381 * descriptors.
382 *
383 * The MXS platform DMA software imposes some rules on DMA commands to maintain
384 * important invariants. These rules are NOT checked, but they must be carefully
385 * applied by software that uses MXS DMA channels.
386 *
387 * Invariant:
388 * The DMA channel's hardware semaphore must reflect the number of DMA
389 * commands the hardware will process, but has not yet finished.
390 *
391 * Explanation:
392 * A DMA channel begins processing commands when its hardware semaphore is
393 * written with a value greater than zero, and it stops processing commands
394 * when the semaphore returns to zero.
395 *
396 * When a channel finishes a DMA command, it will decrement its semaphore if
397 * the DECREMENT_SEMAPHORE bit is set in that command's flags bits.
398 *
399 * In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set,
400 * unless it suits the purposes of the software. For example, one could
401 * construct a series of five DMA commands, with the DECREMENT_SEMAPHORE
402 * bit set only in the last one. Then, setting the DMA channel's hardware
403 * semaphore to one would cause the entire series of five commands to be
404 * processed. However, this example would violate the invariant given above.
405 *
406 * Rule:
407 * ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA
408 * channel's hardware semaphore will be decremented EVERY time a command is
409 * processed.
410 */
411int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc)
412{
413 struct mxs_dma_chan *pchan;
414 struct mxs_dma_desc *last;
415 int ret;
416
417 ret = mxs_dma_validate_chan(channel);
418 if (ret)
419 return ret;
420
421 pchan = mxs_dma_channels + channel;
422
423 pdesc->cmd.next = mxs_dma_cmd_address(pdesc);
424 pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST;
425
426 if (!list_empty(&pchan->active)) {
427 last = list_entry(pchan->active.prev, struct mxs_dma_desc,
428 node);
429
430 pdesc->flags &= ~MXS_DMA_DESC_FIRST;
431 last->flags &= ~MXS_DMA_DESC_LAST;
432
433 last->cmd.next = mxs_dma_cmd_address(pdesc);
434 last->cmd.data |= MXS_DMA_DESC_CHAIN;
Marek Vasutc3dfe702012-03-15 18:33:18 +0000435
436 mxs_dma_flush_desc(last);
Marek Vasut31650d62011-11-08 23:18:15 +0000437 }
438 pdesc->flags |= MXS_DMA_DESC_READY;
439 if (pdesc->flags & MXS_DMA_DESC_FIRST)
440 pchan->pending_num++;
441 list_add_tail(&pdesc->node, &pchan->active);
442
Marek Vasutc3dfe702012-03-15 18:33:18 +0000443 mxs_dma_flush_desc(pdesc);
444
Marek Vasut31650d62011-11-08 23:18:15 +0000445 return ret;
446}
447
448/*
Marek Vasut31650d62011-11-08 23:18:15 +0000449 * Clean up processed DMA descriptors.
450 *
451 * This function removes processed DMA descriptors from the "active" list. Pass
452 * in a non-NULL list head to get the descriptors moved to your list. Pass NULL
453 * to get the descriptors moved to the channel's "done" list. Descriptors on
454 * the "done" list can be retrieved with mxs_dma_get_finished().
455 *
456 * This function marks the DMA channel as "not busy" if no unprocessed
457 * descriptors remain on the "active" list.
458 */
Marek Vasutaa72e432011-11-23 10:59:13 +0000459static int mxs_dma_finish(int channel, struct list_head *head)
Marek Vasut31650d62011-11-08 23:18:15 +0000460{
461 int sem;
462 struct mxs_dma_chan *pchan;
463 struct list_head *p, *q;
464 struct mxs_dma_desc *pdesc;
465 int ret;
466
467 ret = mxs_dma_validate_chan(channel);
468 if (ret)
469 return ret;
470
471 pchan = mxs_dma_channels + channel;
472
473 sem = mxs_dma_read_semaphore(channel);
474 if (sem < 0)
475 return sem;
476
477 if (sem == pchan->active_num)
478 return 0;
479
480 list_for_each_safe(p, q, &pchan->active) {
481 if ((pchan->active_num) <= sem)
482 break;
483
484 pdesc = list_entry(p, struct mxs_dma_desc, node);
485 pdesc->flags &= ~MXS_DMA_DESC_READY;
486
487 if (head)
488 list_move_tail(p, head);
489 else
490 list_move_tail(p, &pchan->done);
491
492 if (pdesc->flags & MXS_DMA_DESC_LAST)
493 pchan->active_num--;
494 }
495
496 if (sem == 0)
497 pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
498
499 return 0;
500}
501
502/*
503 * Wait for DMA channel to complete
504 */
Marek Vasutaa72e432011-11-23 10:59:13 +0000505static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
Marek Vasut31650d62011-11-08 23:18:15 +0000506{
507 struct mx28_apbh_regs *apbh_regs =
508 (struct mx28_apbh_regs *)MXS_APBH_BASE;
509 int ret;
510
511 ret = mxs_dma_validate_chan(chan);
512 if (ret)
513 return ret;
514
515 if (mx28_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,
516 1 << chan, timeout)) {
517 ret = -ETIMEDOUT;
518 mxs_dma_reset(chan);
519 }
520
Wolfram Sang12dab4c2011-11-18 01:17:44 +0000521 return ret;
Marek Vasut31650d62011-11-08 23:18:15 +0000522}
523
524/*
525 * Execute the DMA channel
526 */
527int mxs_dma_go(int chan)
528{
529 uint32_t timeout = 10000;
530 int ret;
531
532 LIST_HEAD(tmp_desc_list);
533
534 mxs_dma_enable_irq(chan, 1);
535 mxs_dma_enable(chan);
536
537 /* Wait for DMA to finish. */
538 ret = mxs_dma_wait_complete(timeout, chan);
539
540 /* Clear out the descriptors we just ran. */
541 mxs_dma_finish(chan, &tmp_desc_list);
542
543 /* Shut the DMA channel down. */
544 mxs_dma_ack_irq(chan);
545 mxs_dma_reset(chan);
546 mxs_dma_enable_irq(chan, 0);
547 mxs_dma_disable(chan);
548
549 return ret;
550}
551
552/*
553 * Initialize the DMA hardware
554 */
Marek Vasut96666a32012-04-08 17:34:46 +0000555void mxs_dma_init(void)
Marek Vasut31650d62011-11-08 23:18:15 +0000556{
557 struct mx28_apbh_regs *apbh_regs =
558 (struct mx28_apbh_regs *)MXS_APBH_BASE;
Marek Vasut31650d62011-11-08 23:18:15 +0000559
560 mx28_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
561
562#ifdef CONFIG_APBH_DMA_BURST8
563 writel(APBH_CTRL0_AHB_BURST8_EN,
564 &apbh_regs->hw_apbh_ctrl0_set);
565#else
566 writel(APBH_CTRL0_AHB_BURST8_EN,
567 &apbh_regs->hw_apbh_ctrl0_clr);
568#endif
569
570#ifdef CONFIG_APBH_DMA_BURST
571 writel(APBH_CTRL0_APB_BURST_EN,
572 &apbh_regs->hw_apbh_ctrl0_set);
573#else
574 writel(APBH_CTRL0_APB_BURST_EN,
575 &apbh_regs->hw_apbh_ctrl0_clr);
576#endif
Marek Vasut96666a32012-04-08 17:34:46 +0000577}
Marek Vasut31650d62011-11-08 23:18:15 +0000578
Marek Vasut96666a32012-04-08 17:34:46 +0000579int mxs_dma_init_channel(int channel)
580{
581 struct mxs_dma_chan *pchan;
582 int ret;
Marek Vasut31650d62011-11-08 23:18:15 +0000583
Marek Vasut96666a32012-04-08 17:34:46 +0000584 pchan = mxs_dma_channels + channel;
585 pchan->flags = MXS_DMA_FLAGS_VALID;
Marek Vasut31650d62011-11-08 23:18:15 +0000586
Marek Vasut96666a32012-04-08 17:34:46 +0000587 ret = mxs_dma_request(channel);
Marek Vasut31650d62011-11-08 23:18:15 +0000588
Marek Vasut96666a32012-04-08 17:34:46 +0000589 if (ret) {
590 printf("MXS DMA: Can't acquire DMA channel %i\n",
591 channel);
592 return ret;
Marek Vasut31650d62011-11-08 23:18:15 +0000593 }
594
Marek Vasut96666a32012-04-08 17:34:46 +0000595 mxs_dma_reset(channel);
596 mxs_dma_ack_irq(channel);
Marek Vasut31650d62011-11-08 23:18:15 +0000597
Marek Vasut96666a32012-04-08 17:34:46 +0000598 return 0;
Marek Vasut31650d62011-11-08 23:18:15 +0000599}