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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
York Sunf749db32014-06-23 15:15:56 -07002/*
Priyanka Jain89a168f2017-04-28 10:41:35 +05303 * Copyright 2017 NXP
York Sunf749db32014-06-23 15:15:56 -07004 * Copyright (C) 2014 Freescale Semiconductor
York Sunf749db32014-06-23 15:15:56 -07005 */
6
7#ifndef __LS2_COMMON_H
8#define __LS2_COMMON_H
9
York Sunf749db32014-06-23 15:15:56 -070010#define CONFIG_REMAKE_ELF
Mingkai Hu9f3183d2015-10-26 19:47:50 +080011#define CONFIG_FSL_LAYERSCAPE
York Sunf749db32014-06-23 15:15:56 -070012#define CONFIG_GICV3
Bhupesh Sharma9c66ce62015-01-06 13:11:21 -080013#define CONFIG_FSL_TZPC_BP147
York Sunf749db32014-06-23 15:15:56 -070014
Bharat Bhushan08c51302017-03-22 12:06:25 +053015#include <asm/arch/stream_id_lsch3.h>
Mingkai Hu9f3183d2015-10-26 19:47:50 +080016#include <asm/arch/config.h>
Minghuan Lian31d34c62015-03-20 19:28:16 -070017
Mingkai Hu9f3183d2015-10-26 19:47:50 +080018/* Link Definitions */
19#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
20
Bhupesh Sharma422cb082015-03-19 09:20:43 -070021/* We need architecture specific misc initializations */
Bhupesh Sharma422cb082015-03-19 09:20:43 -070022
York Sunf749db32014-06-23 15:15:56 -070023/* Link Definitions */
Yuan Yaoa646f662016-06-08 18:25:00 +080024#ifndef CONFIG_QSPI_BOOT
Scott Woodb2d5ac52015-03-24 13:25:02 -070025#else
Priyanka Jain89a168f2017-04-28 10:41:35 +053026#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
27#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
Santan Kumar1c83df62017-08-09 10:35:45 +053028#define CONFIG_ENV_SECT_SIZE 0x40000
Yuan Yaoa646f662016-06-08 18:25:00 +080029#endif
York Sunf749db32014-06-23 15:15:56 -070030
York Sunf749db32014-06-23 15:15:56 -070031#define CONFIG_SKIP_LOWLEVEL_INIT
York Sunf749db32014-06-23 15:15:56 -070032
Scott Woodb2d5ac52015-03-24 13:25:02 -070033#ifndef CONFIG_SPL
York Sunf749db32014-06-23 15:15:56 -070034#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
Scott Woodb2d5ac52015-03-24 13:25:02 -070035#endif
York Sunf749db32014-06-23 15:15:56 -070036#ifndef CONFIG_SYS_FSL_DDR4
York Sunf749db32014-06-23 15:15:56 -070037#define CONFIG_SYS_DDR_RAW_TIMING
38#endif
York Sunf749db32014-06-23 15:15:56 -070039
40#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
41
Mingkai Hu9f3183d2015-10-26 19:47:50 +080042#define CONFIG_VERY_BIG_RAM
York Sunf749db32014-06-23 15:15:56 -070043#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
44#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
45#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
46#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
York Sund9c68b12014-08-13 10:21:05 -070047#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
48
York Sun8bfa3012014-09-08 12:20:01 -070049/*
50 * SMP Definitinos
51 */
52#define CPU_RELEASE_ADDR secondary_boot_func
53
York Sund9c68b12014-08-13 10:21:05 -070054#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053055#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Sund9c68b12014-08-13 10:21:05 -070056#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
57/*
58 * DDR controller use 0 as the base address for binding.
59 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
60 */
61#define CONFIG_SYS_DP_DDR_BASE_PHY 0
62#define CONFIG_DP_DDR_CTRL 2
63#define CONFIG_DP_DDR_NUM_CTRLS 1
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053064#endif
York Sunf749db32014-06-23 15:15:56 -070065
66/* Generic Timer Definitions */
York Sun207774b2015-03-20 19:28:08 -070067/*
68 * This is not an accurate number. It is used in start.S. The frequency
69 * will be udpated later when get_bus_freq(0) is available.
70 */
71#define COUNTER_FREQUENCY 25000000 /* 25MHz */
York Sunf749db32014-06-23 15:15:56 -070072
73/* Size of malloc() pool */
Prabhakar Kushwahaaa66acb2015-03-19 09:20:47 -070074#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
York Sunf749db32014-06-23 15:15:56 -070075
76/* I2C */
York Sunf749db32014-06-23 15:15:56 -070077#define CONFIG_SYS_I2C
York Sunf749db32014-06-23 15:15:56 -070078
79/* Serial Port */
York Sunf749db32014-06-23 15:15:56 -070080#define CONFIG_SYS_NS16550_SERIAL
81#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang35642082017-01-10 16:44:16 +080082#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
York Sunf749db32014-06-23 15:15:56 -070083
York Sunf749db32014-06-23 15:15:56 -070084#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
85
86/* IFC */
87#define CONFIG_FSL_IFC
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -070088
York Sunf749db32014-06-23 15:15:56 -070089/*
York Sun7288c2c2015-03-20 19:28:23 -070090 * During booting, IFC is mapped at the region of 0x30000000.
91 * But this region is limited to 256MB. To accommodate NOR, promjet
92 * and FPGA. This region is divided as below:
93 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
94 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
95 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
96 *
97 * To accommodate bigger NOR flash and other devices, we will map IFC
98 * chip selects to as below:
99 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
100 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
101 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
102 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
103 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
104 *
105 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
York Sunf749db32014-06-23 15:15:56 -0700106 * CONFIG_SYS_FLASH_BASE has the final address (core view)
107 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
108 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
109 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
110 */
York Sun7288c2c2015-03-20 19:28:23 -0700111
York Sunf749db32014-06-23 15:15:56 -0700112#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
113#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
114#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
115
York Sun7288c2c2015-03-20 19:28:23 -0700116#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
117#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
118
York Sun7288c2c2015-03-20 19:28:23 -0700119#ifndef __ASSEMBLY__
120unsigned long long get_qixis_addr(void);
121#endif
122#define QIXIS_BASE get_qixis_addr()
123#define QIXIS_BASE_PHYS 0x20000000
124#define QIXIS_BASE_PHYS_EARLY 0xC000000
Yangbo Lu8b064602015-03-20 19:28:31 -0700125#define QIXIS_STAT_PRES1 0xb
126#define QIXIS_SDID_MASK 0x07
127#define QIXIS_ESDHC_NO_ADAPTER 0x7
York Sun7288c2c2015-03-20 19:28:23 -0700128
129#define CONFIG_SYS_NAND_BASE 0x530000000ULL
130#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
Prabhakar Kushwahae211c122014-07-16 09:21:12 +0530131
York Sunf749db32014-06-23 15:15:56 -0700132/* MC firmware */
York Sunf749db32014-06-23 15:15:56 -0700133/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
J. German Rivera125e2bc2015-03-20 19:28:18 -0700134#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
135#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
136#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
137#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
York Sun3c1d2182016-04-04 11:41:26 -0700138/* For LS2085A */
J. German Riverac1000c12015-07-02 11:28:58 +0530139#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
140#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
York Sunf749db32014-06-23 15:15:56 -0700141
Bogdan Purcareata33a89912017-05-24 16:40:21 +0000142/* Define phy_reset function to boot the MC based on mcinitcmd.
143 * This happens late enough to properly fixup u-boot env MAC addresses.
144 */
145#define CONFIG_RESET_PHY_R
146
Prabhakar Kushwaha5c055082015-06-02 10:55:52 +0530147/*
148 * Carve out a DDR region which will not be used by u-boot/Linux
149 *
150 * It will be used by MC and Debug Server. The MC region must be
151 * 512MB aligned, so the min size to hide is 512MB.
152 */
York Sunb63a9502016-08-03 12:33:00 -0700153#ifdef CONFIG_FSL_MC_ENET
Pratiyush Mohan Srivastava52c11d42015-12-22 16:49:34 +0530154#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
York Sunf749db32014-06-23 15:15:56 -0700155#endif
156
157/* Command line configuration */
York Sunf749db32014-06-23 15:15:56 -0700158
159/* Miscellaneous configurable options */
160#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
161
162/* Physical Memory Map */
163/* fixme: these need to be checked against the board */
164#define CONFIG_CHIP_SELECTS_PER_CTRL 4
York Sunf749db32014-06-23 15:15:56 -0700165
York Sunf749db32014-06-23 15:15:56 -0700166#define CONFIG_HWCONFIG
167#define HWCONFIG_BUFFER_SIZE 128
168
Alison Wang1d3a76f2015-11-13 16:49:06 +0800169/* Allow to overwrite serial and ethaddr */
170#define CONFIG_ENV_OVERWRITE
171
York Sunf749db32014-06-23 15:15:56 -0700172/* Initial environment variables */
173#define CONFIG_EXTRA_ENV_SETTINGS \
174 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
175 "loadaddr=0x80100000\0" \
176 "kernel_addr=0x100000\0" \
177 "ramdisk_addr=0x800000\0" \
178 "ramdisk_size=0x2000000\0" \
Prabhakar Kushwahaf3f8c562015-03-20 19:28:06 -0700179 "fdt_high=0xa0000000\0" \
York Sunf749db32014-06-23 15:15:56 -0700180 "initrd_high=0xffffffffffffffff\0" \
Santan Kumarf5bf23d2017-04-28 12:47:24 +0530181 "kernel_start=0x581000000\0" \
Stuart Yoder052ddd52015-01-06 13:18:57 -0800182 "kernel_load=0xa0000000\0" \
Prabhakar Kushwaha97421bd2015-07-01 16:28:22 +0530183 "kernel_size=0x2800000\0" \
Prabhakar Kushwaha16ed8562016-02-03 17:03:51 +0530184 "console=ttyAMA0,38400n8\0" \
Santan Kumarf5bf23d2017-04-28 12:47:24 +0530185 "mcinitcmd=fsl_mc start mc 0x580a00000" \
186 " 0x580e00000 \0"
York Sunf749db32014-06-23 15:15:56 -0700187
Santan Kumar1f55a932017-05-05 15:42:29 +0530188#ifdef CONFIG_SD_BOOT
189#define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\
190 " fsl_mc apply dpl 0x80200000 &&" \
191 " mmc read $kernel_load $kernel_start" \
192 " $kernel_size && bootm $kernel_load"
193#else
Santan Kumarf5bf23d2017-04-28 12:47:24 +0530194#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
Prabhakar Kushwaha9f3e1b82016-02-03 17:04:07 +0530195 " cp.b $kernel_start $kernel_load" \
196 " $kernel_size && bootm $kernel_load"
Santan Kumar1f55a932017-05-05 15:42:29 +0530197#endif
York Sunf749db32014-06-23 15:15:56 -0700198
York Sunf749db32014-06-23 15:15:56 -0700199/* Monitor Command Prompt */
200#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
York Sunf749db32014-06-23 15:15:56 -0700201#define CONFIG_SYS_MAXARGS 64 /* max command args */
202
Scott Woodb2d5ac52015-03-24 13:25:02 -0700203#define CONFIG_SPL_BSS_START_ADDR 0x80100000
204#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
Scott Woodb2d5ac52015-03-24 13:25:02 -0700205#define CONFIG_SPL_MAX_SIZE 0x16000
Scott Woodb2d5ac52015-03-24 13:25:02 -0700206#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
Jagdish Gediya4b5892c2018-08-23 22:53:33 +0530207#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Scott Woodb2d5ac52015-03-24 13:25:02 -0700208#define CONFIG_SPL_TEXT_BASE 0x1800a000
209
Santan Kumarfaed6bd2017-05-05 15:42:28 +0530210#ifdef CONFIG_NAND_BOOT
Scott Woodb2d5ac52015-03-24 13:25:02 -0700211#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
212#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
Santan Kumarfaed6bd2017-05-05 15:42:28 +0530213#endif
Scott Woodb2d5ac52015-03-24 13:25:02 -0700214#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
215#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
York Sun63143a52017-12-18 08:24:55 -0800216#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
Scott Woodb2d5ac52015-03-24 13:25:02 -0700217
Bhupesh Sharma34cc7542015-05-28 14:54:02 +0530218#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
219
Simon Glass457e51c2017-05-17 08:23:10 -0600220#include <asm/arch/soc.h>
221
York Sunf749db32014-06-23 15:15:56 -0700222#endif /* __LS2_COMMON_H */