blob: a846e0a1fe00fdfd03a183dade8c920a4804769a [file] [log] [blame]
Rayagonda Kokatanur956d57a2020-04-08 11:12:27 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Broadcom
4 *
5 */
6
7#include <asm/io.h>
8#include <common.h>
9#include <config.h>
10#include <dm.h>
11#include "errno.h"
12#include <i2c.h>
13#include "iproc_i2c.h"
14
15DECLARE_GLOBAL_DATA_PTR;
16
17struct iproc_i2c_regs {
18 u32 cfg_reg;
19 u32 timg_cfg;
20 u32 addr_reg;
21 u32 mstr_fifo_ctrl;
22 u32 slv_fifo_ctrl;
23 u32 bitbng_ctrl;
24 u32 blnks[6]; /* Not to be used */
25 u32 mstr_cmd;
26 u32 slv_cmd;
27 u32 evt_en;
28 u32 evt_sts;
29 u32 mstr_datawr;
30 u32 mstr_datard;
31 u32 slv_datawr;
32 u32 slv_datard;
33};
34
35struct iproc_i2c {
36 struct iproc_i2c_regs __iomem *base; /* register base */
37 int bus_speed;
38 int i2c_init_done;
39};
40
41/* Function to read a value from specified register. */
42static unsigned int iproc_i2c_reg_read(u32 *reg_addr)
43{
44 unsigned int val;
45
46 val = readl((void *)(reg_addr));
47 return cpu_to_le32(val);
48}
49
50/* Function to write a value ('val') in to a specified register. */
51static int iproc_i2c_reg_write(u32 *reg_addr, unsigned int val)
52{
53 val = cpu_to_le32(val);
54 writel(val, (void *)(reg_addr));
55 return 0;
56}
57
58#if defined(DEBUG)
59static int iproc_dump_i2c_regs(struct iproc_i2c *bus_prvdata)
60{
61 struct iproc_i2c_regs *base = bus_prvdata->base;
62 unsigned int regval;
63
64 debug("\n----------------------------------------------\n");
65 debug("%s: Dumping SMBus registers...\n", __func__);
66
67 regval = iproc_i2c_reg_read(&base->cfg_reg);
68 debug("CCB_SMB_CFG_REG=0x%08X\n", regval);
69
70 regval = iproc_i2c_reg_read(&base->timg_cfg);
71 debug("CCB_SMB_TIMGCFG_REG=0x%08X\n", regval);
72
73 regval = iproc_i2c_reg_read(&base->addr_reg);
74 debug("CCB_SMB_ADDR_REG=0x%08X\n", regval);
75
76 regval = iproc_i2c_reg_read(&base->mstr_fifo_ctrl);
77 debug("CCB_SMB_MSTRFIFOCTL_REG=0x%08X\n", regval);
78
79 regval = iproc_i2c_reg_read(&base->slv_fifo_ctrl);
80 debug("CCB_SMB_SLVFIFOCTL_REG=0x%08X\n", regval);
81
82 regval = iproc_i2c_reg_read(&base->bitbng_ctrl);
83 debug("CCB_SMB_BITBANGCTL_REG=0x%08X\n", regval);
84
85 regval = iproc_i2c_reg_read(&base->mstr_cmd);
86 debug("CCB_SMB_MSTRCMD_REG=0x%08X\n", regval);
87
88 regval = iproc_i2c_reg_read(&base->slv_cmd);
89 debug("CCB_SMB_SLVCMD_REG=0x%08X\n", regval);
90
91 regval = iproc_i2c_reg_read(&base->evt_en);
92 debug("CCB_SMB_EVTEN_REG=0x%08X\n", regval);
93
94 regval = iproc_i2c_reg_read(&base->evt_sts);
95 debug("CCB_SMB_EVTSTS_REG=0x%08X\n", regval);
96
97 regval = iproc_i2c_reg_read(&base->mstr_datawr);
98 debug("CCB_SMB_MSTRDATAWR_REG=0x%08X\n", regval);
99
100 regval = iproc_i2c_reg_read(&base->mstr_datard);
101 debug("CCB_SMB_MSTRDATARD_REG=0x%08X\n", regval);
102
103 regval = iproc_i2c_reg_read(&base->slv_datawr);
104 debug("CCB_SMB_SLVDATAWR_REG=0x%08X\n", regval);
105
106 regval = iproc_i2c_reg_read(&base->slv_datard);
107 debug("CCB_SMB_SLVDATARD_REG=0x%08X\n", regval);
108
109 debug("----------------------------------------------\n\n");
110 return 0;
111}
112#else
113static int iproc_dump_i2c_regs(struct iproc_i2c *bus_prvdata)
114{
115 return 0;
116}
117#endif
118
119/*
120 * Function to ensure that the previous transaction was completed before
121 * initiating a new transaction. It can also be used in polling mode to
122 * check status of completion of a command
123 */
124static int iproc_i2c_startbusy_wait(struct iproc_i2c *bus_prvdata)
125{
126 struct iproc_i2c_regs *base = bus_prvdata->base;
127 unsigned int regval;
128
129 regval = iproc_i2c_reg_read(&base->mstr_cmd);
130
131 /* Check if an operation is in progress. During probe it won't be.
132 * But when shutdown/remove was called we want to make sure that
133 * the transaction in progress completed
134 */
135 if (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
136 unsigned int i = 0;
137
138 do {
139 mdelay(10);
140 i++;
141 regval = iproc_i2c_reg_read(&base->mstr_cmd);
142
143 /* If start-busy bit cleared, exit the loop */
144 } while ((regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) &&
145 (i < IPROC_SMB_MAX_RETRIES));
146
147 if (i >= IPROC_SMB_MAX_RETRIES) {
148 pr_err("%s: START_BUSY bit didn't clear, exiting\n",
149 __func__);
150 return -ETIMEDOUT;
151 }
152 }
153 return 0;
154}
155
156/*
157 * This function set clock frequency for SMBus block. As per hardware
158 * engineering, the clock frequency can be changed dynamically.
159 */
160static int iproc_i2c_set_clk_freq(struct iproc_i2c *bus_prvdata)
161{
162 struct iproc_i2c_regs *base = bus_prvdata->base;
163 unsigned int regval;
164
165 regval = iproc_i2c_reg_read(&base->timg_cfg);
166
167 switch (bus_prvdata->bus_speed) {
168 case I2C_SPEED_STANDARD_RATE:
169 regval &= ~CCB_SMB_TIMGCFG_MODE400_MASK;
170 break;
171
172 case I2C_SPEED_FAST_RATE:
173 regval |= CCB_SMB_TIMGCFG_MODE400_MASK;
174 break;
175
176 default:
177 return -EINVAL;
178 }
179
180 iproc_i2c_reg_write(&base->timg_cfg, regval);
181 return 0;
182}
183
184static int iproc_i2c_init(struct udevice *bus)
185{
186 struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
187 struct iproc_i2c_regs *base = bus_prvdata->base;
188 unsigned int regval;
189
190 debug("\nEntering %s\n", __func__);
191
192 /* Put controller in reset */
193 regval = iproc_i2c_reg_read(&base->cfg_reg);
194 regval |= CCB_SMB_CFG_RST_MASK;
195 regval &= ~CCB_SMB_CFG_SMBEN_MASK;
196 iproc_i2c_reg_write(&base->cfg_reg, regval);
197
198 /* Wait 100 usec as per spec */
199 udelay(100);
200
201 /* bring controller out of reset */
202 regval &= ~CCB_SMB_CFG_RST_MASK;
203 iproc_i2c_reg_write(&base->cfg_reg, regval);
204
205 /* Flush Tx, Rx FIFOs. Note we are setting the Rx FIFO threshold to 0.
206 * May be OK since we are setting RX_EVENT and RX_FIFO_FULL interrupts
207 */
208 regval = CCB_SMB_MSTRRXFIFOFLSH_MASK | CCB_SMB_MSTRTXFIFOFLSH_MASK;
209 iproc_i2c_reg_write(&base->mstr_fifo_ctrl, regval);
210
211 /* Enable SMbus block. Note, we are setting MASTER_RETRY_COUNT to zero
212 * since there will be only one master
213 */
214 regval = iproc_i2c_reg_read(&base->cfg_reg);
215 regval |= CCB_SMB_CFG_SMBEN_MASK;
216 iproc_i2c_reg_write(&base->cfg_reg, regval);
217
218 /* Set default clock frequency */
219 iproc_i2c_set_clk_freq(bus_prvdata);
220
221 /* Disable intrs */
222 iproc_i2c_reg_write(&base->evt_en, 0);
223
224 /* Clear intrs (W1TC) */
225 regval = iproc_i2c_reg_read(&base->evt_sts);
226 iproc_i2c_reg_write(&base->evt_sts, regval);
227
228 bus_prvdata->i2c_init_done = 1;
229
230 iproc_dump_i2c_regs(bus_prvdata);
231 debug("%s: Init successful\n", __func__);
232
233 return 0;
234}
235
236/*
237 * This function copies data to SMBus's Tx FIFO. Valid for write transactions
238 * only
239 *
240 * base_addr: Mapped address of this SMBus instance
241 * dev_addr: SMBus (I2C) device address. We are assuming 7-bit addresses
242 * initially
243 * info: Data to copy in to Tx FIFO. For read commands, the size should be
244 * set to zero by the caller
245 *
246 */
247static void iproc_i2c_write_trans_data(struct iproc_i2c *bus_prvdata,
248 unsigned short dev_addr,
249 struct iproc_xact_info *info)
250{
251 struct iproc_i2c_regs *base = bus_prvdata->base;
252 unsigned int regval;
253 unsigned int i;
254 unsigned int num_data_bytes = 0;
255
256 debug("%s: dev_addr=0x%X cmd_valid=%d cmd=0x%02x size=%u proto=%d buf[] %x\n",
257 __func__, dev_addr, info->cmd_valid,
258 info->command, info->size, info->smb_proto, info->data[0]);
259
260 /* Write SMBus device address first */
261 /* Note, we are assuming 7-bit addresses for now. For 10-bit addresses,
262 * we may have one more write to send the upper 3 bits of 10-bit addr
263 */
264 iproc_i2c_reg_write(&base->mstr_datawr, dev_addr);
265
266 /* If the protocol needs command code, copy it */
267 if (info->cmd_valid)
268 iproc_i2c_reg_write(&base->mstr_datawr, info->command);
269
270 /* Depending on the SMBus protocol, we need to write additional
271 * transaction data in to Tx FIFO. Refer to section 5.5 of SMBus
272 * spec for sequence for a transaction
273 */
274 switch (info->smb_proto) {
275 case SMBUS_PROT_RECV_BYTE:
276 /* No additional data to be written */
277 num_data_bytes = 0;
278 break;
279
280 case SMBUS_PROT_SEND_BYTE:
281 num_data_bytes = info->size;
282 break;
283
284 case SMBUS_PROT_RD_BYTE:
285 case SMBUS_PROT_RD_WORD:
286 case SMBUS_PROT_BLK_RD:
287 /* Write slave address with R/W~ set (bit #0) */
288 iproc_i2c_reg_write(&base->mstr_datawr,
289 dev_addr | 0x1);
290 num_data_bytes = 0;
291 break;
292
293 case SMBUS_PROT_BLK_WR_BLK_RD_PROC_CALL:
294 iproc_i2c_reg_write(&base->mstr_datawr,
295 dev_addr | 0x1 |
296 CCB_SMB_MSTRWRSTS_MASK);
297 num_data_bytes = 0;
298 break;
299
300 case SMBUS_PROT_WR_BYTE:
301 case SMBUS_PROT_WR_WORD:
302 /* No additional bytes to be written.
303 * Data portion is written in the
304 * 'for' loop below
305 */
306 num_data_bytes = info->size;
307 break;
308
309 case SMBUS_PROT_BLK_WR:
310 /* 3rd byte is byte count */
311 iproc_i2c_reg_write(&base->mstr_datawr, info->size);
312 num_data_bytes = info->size;
313 break;
314
315 default:
316 return;
317 }
318
319 /* Copy actual data from caller, next. In general, for reads,
320 * no data is copied
321 */
322 for (i = 0; num_data_bytes; --num_data_bytes, i++) {
323 /* For the last byte, set MASTER_WR_STATUS bit */
324 regval = (num_data_bytes == 1) ?
325 info->data[i] | CCB_SMB_MSTRWRSTS_MASK :
326 info->data[i];
327
328 iproc_i2c_reg_write(&base->mstr_datawr, regval);
329 }
330}
331
332static int iproc_i2c_data_send(struct iproc_i2c *bus_prvdata,
333 unsigned short addr,
334 struct iproc_xact_info *info)
335{
336 struct iproc_i2c_regs *base = bus_prvdata->base;
337 int rc, retry = 3;
338 unsigned int regval;
339
340 /* Make sure the previous transaction completed */
341 rc = iproc_i2c_startbusy_wait(bus_prvdata);
342
343 if (rc < 0) {
344 pr_err("%s: Send: bus is busy, exiting\n", __func__);
345 return rc;
346 }
347
348 /* Write transaction bytes to Tx FIFO */
349 iproc_i2c_write_trans_data(bus_prvdata, addr, info);
350
351 /* Program master command register (0x30) with protocol type and set
352 * start_busy_command bit to initiate the write transaction
353 */
354 regval = (info->smb_proto << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
355 CCB_SMB_MSTRSTARTBUSYCMD_MASK;
356
357 iproc_i2c_reg_write(&base->mstr_cmd, regval);
358
359 /* Check for Master status */
360 regval = iproc_i2c_reg_read(&base->mstr_cmd);
361 while (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
362 mdelay(10);
363 if (retry-- <= 0)
364 break;
365 regval = iproc_i2c_reg_read(&base->mstr_cmd);
366 }
367
368 /* If start_busy bit cleared, check if there are any errors */
369 if (!(regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK)) {
370 /* start_busy bit cleared, check master_status field now */
371 regval &= CCB_SMB_MSTRSTS_MASK;
372 regval >>= CCB_SMB_MSTRSTS_SHIFT;
373
374 if (regval != MSTR_STS_XACT_SUCCESS) {
375 /* Error We can flush Tx FIFO here */
376 pr_err("%s: ERROR: Error in transaction %u, exiting\n",
377 __func__, regval);
378 return -EREMOTEIO;
379 }
380 }
381
382 return 0;
383}
384
385static int iproc_i2c_data_recv(struct iproc_i2c *bus_prvdata,
386 unsigned short addr,
387 struct iproc_xact_info *info,
388 unsigned int *num_bytes_read)
389{
390 struct iproc_i2c_regs *base = bus_prvdata->base;
391 int rc, retry = 3;
392 unsigned int regval;
393
394 /* Make sure the previous transaction completed */
395 rc = iproc_i2c_startbusy_wait(bus_prvdata);
396
397 if (rc < 0) {
398 pr_err("%s: Receive: Bus is busy, exiting\n", __func__);
399 return rc;
400 }
401
402 /* Program all transaction bytes into master Tx FIFO */
403 iproc_i2c_write_trans_data(bus_prvdata, addr, info);
404
405 /* Program master command register (0x30) with protocol type and set
406 * start_busy_command bit to initiate the write transaction
407 */
408 regval = (info->smb_proto << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
409 CCB_SMB_MSTRSTARTBUSYCMD_MASK | info->size;
410
411 iproc_i2c_reg_write(&base->mstr_cmd, regval);
412
413 /* Check for Master status */
414 regval = iproc_i2c_reg_read(&base->mstr_cmd);
415 while (regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK) {
416 udelay(1000);
417 if (retry-- <= 0)
418 break;
419 regval = iproc_i2c_reg_read(&base->mstr_cmd);
420 }
421
422 /* If start_busy bit cleared, check if there are any errors */
423 if (!(regval & CCB_SMB_MSTRSTARTBUSYCMD_MASK)) {
424 /* start_busy bit cleared, check master_status field now */
425 regval &= CCB_SMB_MSTRSTS_MASK;
426 regval >>= CCB_SMB_MSTRSTS_SHIFT;
427
428 if (regval != MSTR_STS_XACT_SUCCESS) {
429 /* We can flush Tx FIFO here */
430 pr_err("%s: Error in transaction %d, exiting\n",
431 __func__, regval);
432 return -EREMOTEIO;
433 }
434 }
435
436 /* Read received byte(s), after TX out address etc */
437 regval = iproc_i2c_reg_read(&base->mstr_datard);
438
439 /* For block read, protocol (hw) returns byte count,
440 * as the first byte
441 */
442 if (info->smb_proto == SMBUS_PROT_BLK_RD) {
443 int i;
444
445 *num_bytes_read = regval & CCB_SMB_MSTRRDDATA_MASK;
446
447 /* Limit to reading a max of 32 bytes only; just a safeguard.
448 * If # bytes read is a number > 32, check transaction set up,
449 * and contact hw engg. Assumption: PEC is disabled
450 */
451 for (i = 0;
452 (i < *num_bytes_read) && (i < I2C_SMBUS_BLOCK_MAX);
453 i++) {
454 /* Read Rx FIFO for data bytes */
455 regval = iproc_i2c_reg_read(&base->mstr_datard);
456 info->data[i] = regval & CCB_SMB_MSTRRDDATA_MASK;
457 }
458 } else {
459 /* 1 Byte data */
460 *info->data = regval & CCB_SMB_MSTRRDDATA_MASK;
461 *num_bytes_read = 1;
462 }
463
464 return 0;
465}
466
467static int i2c_write_byte(struct iproc_i2c *bus_prvdata,
468 u8 devaddr, u8 regoffset, u8 value)
469{
470 int rc;
471 struct iproc_xact_info info;
472
473 devaddr <<= 1;
474
475 info.cmd_valid = 1;
476 info.command = (unsigned char)regoffset;
477 info.data = &value;
478 info.size = 1;
479 info.flags = 0;
480 info.smb_proto = SMBUS_PROT_WR_BYTE;
481 /* Refer to i2c_smbus_write_byte params passed. */
482 rc = iproc_i2c_data_send(bus_prvdata, devaddr, &info);
483
484 if (rc < 0) {
485 pr_err("%s: %s error accessing device 0x%X\n",
486 __func__, "Write", devaddr);
487 return -EREMOTEIO;
488 }
489
490 return 0;
491}
492
493int i2c_write(struct udevice *bus,
494 uchar chip, uint regaddr, int alen, uchar *buffer, int len)
495{
496 struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
497 int i, data_len;
498 u8 *data;
499
500 if (len > 256) {
501 pr_err("I2C write: address out of range\n");
502 return 1;
503 }
504
505 if (len < 1) {
506 pr_err("I2C write: Need offset addr and value\n");
507 return 1;
508 }
509
510 /* buffer contains offset addr followed by value to be written */
511 regaddr = buffer[0];
512 data = &buffer[1];
513 data_len = len - 1;
514
515 for (i = 0; i < data_len; i++) {
516 if (i2c_write_byte(bus_prvdata, chip, regaddr + i, data[i])) {
517 pr_err("I2C write (%d): I/O error\n", i);
518 iproc_i2c_init(bus);
519 return 1;
520 }
521 }
522
523 return 0;
524}
525
526static int i2c_read_byte(struct iproc_i2c *bus_prvdata,
527 u8 devaddr, u8 regoffset, u8 *value)
528{
529 int rc;
530 struct iproc_xact_info info;
531 unsigned int num_bytes_read = 0;
532
533 devaddr <<= 1;
534
535 info.cmd_valid = 1;
536 info.command = (unsigned char)regoffset;
537 info.data = value;
538 info.size = 1;
539 info.flags = 0;
540 info.smb_proto = SMBUS_PROT_RD_BYTE;
541 /* Refer to i2c_smbus_read_byte for params passed. */
542 rc = iproc_i2c_data_recv(bus_prvdata, devaddr, &info, &num_bytes_read);
543
544 if (rc < 0) {
545 pr_err("%s: %s error accessing device 0x%X\n",
546 __func__, "Read", devaddr);
547 return -EREMOTEIO;
548 }
549
550 return 0;
551}
552
553int i2c_read(struct udevice *bus,
554 uchar chip, uint addr, int alen, uchar *buffer, int len)
555{
556 struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
557 int i;
558
559 if (len > 256) {
560 pr_err("I2C read: address out of range\n");
561 return 1;
562 }
563
564 for (i = 0; i < len; i++) {
565 if (i2c_read_byte(bus_prvdata, chip, addr + i, &buffer[i])) {
566 pr_err("I2C read: I/O error\n");
567 iproc_i2c_init(bus);
568 return 1;
569 }
570 }
571
572 return 0;
573}
574
575static int iproc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
576{
577 int ret = 0;
578
579 debug("%s: %d messages\n", __func__, nmsgs);
580
581 for (; nmsgs > 0; nmsgs--, msg++) {
582 if (msg->flags & I2C_M_RD)
583 ret = i2c_read(bus, msg->addr, 0, 0,
584 msg->buf, msg->len);
585 else
586 ret = i2c_write(bus, msg->addr, 0, 0,
587 msg->buf, msg->len);
588 }
589
590 return ret;
591}
592
593static int iproc_i2c_probe_chip(struct udevice *bus, uint chip_addr,
594 uint chip_flags)
595{
596 struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
597 struct iproc_i2c_regs *base = bus_prvdata->base;
598 u32 regval;
599
600 debug("\n%s: Entering chip probe\n", __func__);
601
602 /* Init internal regs, disable intrs (and then clear intrs), set fifo
603 * thresholds, etc.
604 */
605 if (!bus_prvdata->i2c_init_done)
606 iproc_i2c_init(bus);
607
608 regval = (chip_addr << 1);
609 iproc_i2c_reg_write(&base->mstr_datawr, regval);
610 regval = ((SMBUS_PROT_QUICK_CMD << CCB_SMB_MSTRSMBUSPROTO_SHIFT) |
611 (1 << CCB_SMB_MSTRSTARTBUSYCMD_SHIFT));
612 iproc_i2c_reg_write(&base->mstr_cmd, regval);
613
614 do {
615 udelay(100);
616 regval = iproc_i2c_reg_read(&base->mstr_cmd);
617 regval &= CCB_SMB_MSTRSTARTBUSYCMD_MASK;
618 } while (regval);
619
620 regval = iproc_i2c_reg_read(&base->mstr_cmd);
621
622 if ((regval & CCB_SMB_MSTRSTS_MASK) != 0)
623 return -1;
624
625 iproc_dump_i2c_regs(bus_prvdata);
626 debug("%s: chip probe successful\n", __func__);
627
628 return 0;
629}
630
631static int iproc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
632{
633 struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
634
635 bus_prvdata->bus_speed = speed;
636 return iproc_i2c_set_clk_freq(bus_prvdata);
637}
638
639/**
640 * i2c_get_bus_speed - get i2c bus speed
641 *
642 * This function returns the speed of operation in Hz
643 */
644int iproc_i2c_get_bus_speed(struct udevice *bus)
645{
646 struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
647 struct iproc_i2c_regs *base = bus_prvdata->base;
648 unsigned int regval;
649 int ret = 0;
650
651 regval = iproc_i2c_reg_read(&base->timg_cfg);
652 regval = (regval & CCB_SMB_TIMGCFG_MODE400_MASK) >>
653 CCB_SMB_TIMGCFG_MODE400_SHIFT;
654
655 switch (regval) {
656 case 0:
657 ret = I2C_SPEED_STANDARD_RATE;
658 break;
659 case 1:
660 ret = I2C_SPEED_FAST_RATE;
661 break;
662 default:
663 ret = -EINVAL;
664 break;
665 }
666
667 return ret;
668}
669
670static int iproc_i2c_probe(struct udevice *bus)
671{
672 return iproc_i2c_init(bus);
673}
674
675static int iproc_i2c_ofdata_to_platdata(struct udevice *bus)
676{
677 struct iproc_i2c *bus_prvdata = dev_get_priv(bus);
678 int node = dev_of_offset(bus);
679 const void *blob = gd->fdt_blob;
680
681 bus_prvdata->base = map_physmem(devfdt_get_addr(bus),
682 sizeof(void *),
683 MAP_NOCACHE);
684
685 bus_prvdata->bus_speed =
686 fdtdec_get_int(blob, node, "bus-frequency",
687 I2C_SPEED_STANDARD_RATE);
688
689 return 0;
690}
691
692static const struct dm_i2c_ops iproc_i2c_ops = {
693 .xfer = iproc_i2c_xfer,
694 .probe_chip = iproc_i2c_probe_chip,
695 .set_bus_speed = iproc_i2c_set_bus_speed,
696 .get_bus_speed = iproc_i2c_get_bus_speed,
697};
698
699static const struct udevice_id iproc_i2c_ids[] = {
700 { .compatible = "brcm,iproc-i2c" },
701 { }
702};
703
704U_BOOT_DRIVER(iproc_i2c) = {
705 .name = "iproc_i2c",
706 .id = UCLASS_I2C,
707 .of_match = iproc_i2c_ids,
708 .ofdata_to_platdata = iproc_i2c_ofdata_to_platdata,
709 .probe = iproc_i2c_probe,
710 .priv_auto_alloc_size = sizeof(struct iproc_i2c),
711 .ops = &iproc_i2c_ops,
712 .flags = DM_FLAG_PRE_RELOC,
713};