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angelo@sysam.it06fd66a2015-02-12 01:39:40 +01001/*
2 * Sysam AMCORE board configuration
3 *
4 * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __AMCORE_CONFIG_H
10#define __AMCORE_CONFIG_H
11
12#define CONFIG_AMCORE
13#define CONFIG_HOSTNAME AMCORE
14
angelo@sysam.it06fd66a2015-02-12 01:39:40 +010015#define CONFIG_MCFTMR
16#define CONFIG_MCFUART
17#define CONFIG_SYS_UART_PORT 0
18#define CONFIG_BAUDRATE 115200
19#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
20
21#define CONFIG_BOOTDELAY 1
22#define CONFIG_BOOTCOMMAND "bootm ffc20000"
23
angelo@sysam.it06fd66a2015-02-12 01:39:40 +010024#undef CONFIG_CMD_AES
angelo@sysam.it06fd66a2015-02-12 01:39:40 +010025#define CONFIG_CMD_CACHE
26#define CONFIG_CMD_TIMER
27#define CONFIG_CMD_DIAG
28
29#define CONFIG_SYS_PROMPT "amcore $ "
30/* undef to save memory */
31#undef CONFIG_SYS_LONGHELP
32
33#if defined(CONFIG_CMD_KGDB)
34/* Console I/O buff. size */
35#define CONFIG_SYS_CBSIZE 1024
36#else
37#define CONFIG_SYS_CBSIZE 256
38#endif
39/* Print buffer size */
40#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
41 sizeof(CONFIG_SYS_PROMPT)+16)
42/* max number of command args */
43#define CONFIG_SYS_MAXARGS 16
44/* Boot argument buffer size */
45#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
46
47#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */
48#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
49#define CONFIG_LOOPW 1 /* enable loopw command */
50#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
51
52#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
53
54#define CONFIG_SYS_MEMTEST_START 0x0
55#define CONFIG_SYS_MEMTEST_END 0x1000000
56
57#define CONFIG_SYS_HZ 1000
58
59#define CONFIG_SYS_CLK 45000000
60#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
61/* Register Base Addrs */
62#define CONFIG_SYS_MBAR 0x10000000
63/* Definitions for initial stack pointer and data area (in DPRAM) */
64#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
65/* size of internal SRAM */
66#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
67#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
68 GENERATED_GBL_DATA_SIZE)
69#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
70
71#define CONFIG_SYS_SDRAM_BASE 0x00000000
72#define CONFIG_SYS_SDRAM_SIZE 0x1000000
73#define CONFIG_SYS_FLASH_BASE 0xffc00000
74#define CONFIG_SYS_MAX_FLASH_BANKS 1
75#define CONFIG_SYS_MAX_FLASH_SECT 1024
76#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
77
78#define CONFIG_SYS_FLASH_CFI
79#define CONFIG_FLASH_CFI_DRIVER
80#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
81/* amcore design has flash data bytes wired swapped */
82#define CONFIG_SYS_WRITE_SWAPPED_DATA
83/* reserve 128-4KB */
84#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
85#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
86#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
87#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
88
89#define CONFIG_ENV_IS_IN_FLASH 1
90#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
91 CONFIG_SYS_MONITOR_LEN)
92#define CONFIG_ENV_SIZE 0x1000
93#define CONFIG_ENV_SECT_SIZE 0x1000
94
angelo@sysam.it5296cb12015-03-29 22:54:16 +020095#define LDS_BOARD_TEXT \
96 . = DEFINED(env_offset) ? env_offset : .; \
97 common/env_embedded.o (.text*);
98
angelo@sysam.it06fd66a2015-02-12 01:39:40 +010099/* memory map space for linux boot data */
100#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
101
102/*
103 * Cache Configuration
104 *
105 * Special 8K version 3 core cache.
106 * This is a single unified instruction/data cache.
107 * sdram - single region - no masks
108 */
109#define CONFIG_SYS_CACHELINE_SIZE 16
110
111#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
112 CONFIG_SYS_INIT_RAM_SIZE - 8)
113#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
114 CONFIG_SYS_INIT_RAM_SIZE - 4)
115#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
116#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
117 CF_ACR_EN)
118#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
119 CF_CACR_EC)
120
121/* CS0 - AMD Flash, address 0xffc00000 */
122#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
123/* 4MB, AA=0,V=1 C/I BIT for errata */
124#define CONFIG_SYS_CS0_MASK 0x003f0001
125/* WS=10, AA=1, PS=16bit (10) */
126#define CONFIG_SYS_CS0_CTRL 0x1980
127/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
128#define CONFIG_SYS_CS1_BASE 0x3000
129#define CONFIG_SYS_CS1_MASK 0x00070001
130#define CONFIG_SYS_CS1_CTRL 0x0100
131
132#endif /* __AMCORE_CONFIG_H */
133