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gerrit.cesnet.cz / github / trini / u-boot / 94069301bafb601ff3c61b5d208fba4e3c948efd / . / board / logicpd / imx27lite / lowlevel_init.S
blob: 9cb702f30f3e6b32db89ad79592205bb70b63f1f [file] [log] [blame]
Ilya Yanok10bc2412009-08-11 02:32:09 +0400[diff] [blame]1/*
2 * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
3 * Applications Processor Reference Manual, Rev. 0.2".
4 *
5 * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
6 * (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Ilya Yanok10bc2412009-08-11 02:32:09 +0400[diff] [blame]9 */
10
11
12#include <config.h>
Ilya Yanok10bc2412009-08-11 02:32:09 +0400[diff] [blame]13#include <asm/macro.h>
14#include <asm/arch/imx-regs.h>
Stefano Babica4814a62011-09-05 04:32:28 +0000[diff] [blame]15#include <generated/asm-offsets.h>
Ilya Yanok10bc2412009-08-11 02:32:09 +0400[diff] [blame]16
17SOC_ESDCTL_BASE_W: .word IMX_ESD_BASE
18SOC_SI_ID_REG_W: .word IMX_SYSTEM_CTL_BASE
19SDRAM_ESDCFG_T1_W: .word SDRAM_ESDCFG_REGISTER_VAL(0)
20SDRAM_ESDCFG_T2_W: .word SDRAM_ESDCFG_REGISTER_VAL(3)
21SDRAM_PRECHARGE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
22 ESDCTL_ROW13 | ESDCTL_COL10)
23SDRAM_AUTOREF_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
24 ESDCTL_ROW13 | ESDCTL_COL10)
25SDRAM_LOADMODE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
26 ESDCTL_ROW13 | ESDCTL_COL10)
27SDRAM_NORMAL_CMD_W: .word SDRAM_ESDCTL_REGISTER_VAL
28
29.macro init_aipi
30 /*
31 * setup AIPI1 and AIPI2
32 */
33 write32 AIPI1_PSR0, AIPI1_PSR0_VAL
34 write32 AIPI1_PSR1, AIPI1_PSR1_VAL
35 write32 AIPI2_PSR0, AIPI2_PSR0_VAL
36 write32 AIPI2_PSR1, AIPI2_PSR1_VAL
37
38.endm /* init_aipi */
39
40.macro init_clock
41 ldr r0, =CSCR
42 /* disable MPLL/SPLL first */
43 ldr r1, [r0]
44 bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
45 str r1, [r0]
46
47 write32 MPCTL0, MPCTL0_VAL
48 write32 SPCTL0, SPCTL0_VAL
49
50 write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
51
52 /*
53 * add some delay here
54 */
55 wait_timer 0x1000
56
57 /* peripheral clock divider */
58 write32 PCDR0, PCDR0_VAL
59 write32 PCDR1, PCDR1_VAL
60
61 /* Configure PCCR0 and PCCR1 */
62 write32 PCCR0, PCCR0_VAL
63 write32 PCCR1, PCCR1_VAL
64
65.endm /* init_clock */
66
67.macro sdram_init
68 ldr r0, SOC_ESDCTL_BASE_W
69 mov r2, #PHYS_SDRAM_1
70
71 /* Do initial reset */
72 mov r1, #ESDMISC_MDDR_DL_RST
73 str r1, [r0, #ESDMISC_ROF]
74
75 /* Hold for more than 200ns */
76 wait_timer 0x10000
77
78 /* Activate LPDDR iface */
79 mov r1, #ESDMISC_MDDREN
80 str r1, [r0, #ESDMISC_ROF]
81
82 /* Check The chip version TO1 or TO2 */
83 ldr r1, SOC_SI_ID_REG_W
84 ldr r1, [r1]
85 ands r1, r1, #0xF0000000
86 /* add Latency on CAS only for TO2 */
87 ldreq r1, SDRAM_ESDCFG_T2_W
88 ldrne r1, SDRAM_ESDCFG_T1_W
89 str r1, [r0, #ESDCFG0_ROF]
90
91 /* Run initialization sequence */
92 ldr r1, SDRAM_PRECHARGE_CMD_W
93 str r1, [r0, #ESDCTL0_ROF]
94 ldr r1, [r2, #SDRAM_ALL_VAL]
95
96 ldr r1, SDRAM_AUTOREF_CMD_W
97 str r1, [r0, #ESDCTL0_ROF]
98 ldr r1, [r2, #SDRAM_ALL_VAL]
99 ldr r1, [r2, #SDRAM_ALL_VAL]
100
101 ldr r1, SDRAM_LOADMODE_CMD_W
102 str r1, [r0, #ESDCTL0_ROF]
103 ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
104 add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
105 ldrb r1, [r3]
106
107 ldr r1, SDRAM_NORMAL_CMD_W
108 str r1, [r0, #ESDCTL0_ROF]
109
110#if (CONFIG_NR_DRAM_BANKS > 1)
111 /* 2nd sdram */
112 mov r2, #PHYS_SDRAM_2
113
114 /* Check The chip version TO1 or TO2 */
115 ldr r1, SOC_SI_ID_REG_W
116 ldr r1, [r1]
117 ands r1, r1, #0xF0000000
118 /* add Latency on CAS only for TO2 */
119 ldreq r1, SDRAM_ESDCFG_T2_W
120 ldrne r1, SDRAM_ESDCFG_T1_W
121 str r1, [r0, #ESDCFG1_ROF]
122
123 /* Run initialization sequence */
124 ldr r1, SDRAM_PRECHARGE_CMD_W
125 str r1, [r0, #ESDCTL1_ROF]
126 ldr r1, [r2, #SDRAM_ALL_VAL]
127
128 ldr r1, SDRAM_AUTOREF_CMD_W
129 str r1, [r0, #ESDCTL1_ROF]
130 ldr r1, [r2, #SDRAM_ALL_VAL]
131 ldr r1, [r2, #SDRAM_ALL_VAL]
132
133 ldr r1, SDRAM_LOADMODE_CMD_W
134 str r1, [r0, #ESDCTL1_ROF]
135 ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
136 add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
137 ldrb r1, [r3]
138
139 ldr r1, SDRAM_NORMAL_CMD_W
140 str r1, [r0, #ESDCTL1_ROF]
141#endif /* CONFIG_NR_DRAM_BANKS > 1 */
142
143.endm /* sdram_init */
144
145.globl lowlevel_init
146lowlevel_init:
147
148 mov r10, lr
149
150 init_aipi
151
152 init_clock
153
154 sdram_init
155
156 mov pc,r10