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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +09002/*
3 * board/renesas/alt/alt.c
4 *
Mitsuhiro Kimuracae72042015-03-04 15:57:03 +09005 * Copyright (C) 2014, 2015 Renesas Electronics Corporation
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +09006 */
7
8#include <common.h>
9#include <malloc.h>
Nobuhiro Iwamatsu9e116f62014-12-09 16:20:04 +090010#include <dm.h>
11#include <dm/platform_data/serial_sh.h>
Alex Kiernan9925f1d2018-04-01 09:22:38 +000012#include <environment.h>
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090013#include <asm/processor.h>
14#include <asm/mach-types.h>
15#include <asm/io.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090016#include <linux/errno.h>
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090017#include <asm/arch/sys_proto.h>
18#include <asm/gpio.h>
19#include <asm/arch/rmobile.h>
Nobuhiro Iwamatsu44e1eeb2014-12-02 16:52:19 +090020#include <asm/arch/rcar-mstp.h>
Nobuhiro Iwamatsu2b8c0812014-12-03 15:30:30 +090021#include <asm/arch/mmc.h>
Nobuhiro Iwamatsu25f96132014-11-19 14:26:33 +090022#include <asm/arch/sh_sdhi.h>
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090023#include <netdev.h>
24#include <miiphy.h>
25#include <i2c.h>
26#include <div64.h>
27#include "qos.h"
28
29DECLARE_GLOBAL_DATA_PTR;
30
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090031void s_init(void)
32{
33 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
34 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
35
36 /* Watchdog init */
37 writel(0xA5A5A500, &rwdt->rwtcsra);
38 writel(0xA5A5A500, &swdt->swtcsra);
39
40 /* QoS */
41 qos_init();
42}
43
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020044#define TMU0_MSTP125 BIT(25)
45#define MMC0_MSTP315 BIT(15)
Nobuhiro Iwamatsu25f96132014-11-19 14:26:33 +090046
47#define SD1CKCR 0xE6150078
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020048#define SD_97500KHZ 0x7
Nobuhiro Iwamatsu92ef38e2014-11-10 09:16:43 +090049
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090050int board_early_init_f(void)
51{
52 /* TMU */
53 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
54
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020055 /* Set SD1 to the 97.5MHz */
56 writel(SD_97500KHZ, SD1CKCR);
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090057
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090058 return 0;
59}
60
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020061#define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */
62
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090063int board_init(void)
64{
65 /* adress of boot parameters */
Nobuhiro Iwamatsu47726842014-11-10 13:58:50 +090066 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090067
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020068 /* Force ethernet PHY out of reset */
69 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
70 gpio_direction_output(ETHERNET_PHY_RESET, 0);
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090071 mdelay(20);
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020072 gpio_direction_output(ETHERNET_PHY_RESET, 1);
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090073 udelay(1);
74
75 return 0;
76}
77
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090078int dram_init(void)
79{
Siva Durga Prasad Paladugu12308b12018-07-16 15:56:11 +053080 if (fdtdec_setup_mem_size_base() != 0)
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020081 return -EINVAL;
82
83 return 0;
84}
85
86int dram_init_banksize(void)
87{
88 fdtdec_setup_memory_banksize();
89
90 return 0;
91}
92
93/* KSZ8041RNLI */
94#define PHY_CONTROL1 0x1E
Marek Vasut4bbd4642019-03-30 07:05:09 +010095#define PHY_LED_MODE 0xC000
Marek Vasutbb6d2ff2018-04-23 20:24:16 +020096#define PHY_LED_MODE_ACK 0x4000
97int board_phy_config(struct phy_device *phydev)
98{
99 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
100 ret &= ~PHY_LED_MODE;
101 ret |= PHY_LED_MODE_ACK;
102 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +0900103
104 return 0;
105}
106
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +0900107void reset_cpu(ulong addr)
108{
Marek Vasutbb6d2ff2018-04-23 20:24:16 +0200109 struct udevice *dev;
Marek Vasut0c78ec62019-03-30 08:24:19 +0100110 const u8 pmic_bus = 7;
Marek Vasutbb6d2ff2018-04-23 20:24:16 +0200111 const u8 pmic_addr = 0x58;
112 u8 data;
113 int ret;
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +0900114
Marek Vasutbb6d2ff2018-04-23 20:24:16 +0200115 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
116 if (ret)
117 hang();
118
119 ret = dm_i2c_read(dev, 0x13, &data, 1);
120 if (ret)
121 hang();
122
123 data |= BIT(1);
124
125 ret = dm_i2c_write(dev, 0x13, &data, 1);
126 if (ret)
127 hang();
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +0900128}
Nobuhiro Iwamatsu9e116f62014-12-09 16:20:04 +0900129
Marek Vasutbb6d2ff2018-04-23 20:24:16 +0200130enum env_location env_get_location(enum env_operation op, int prio)
131{
132 const u32 load_magic = 0xb33fc0de;
Nobuhiro Iwamatsu9e116f62014-12-09 16:20:04 +0900133
Marek Vasutbb6d2ff2018-04-23 20:24:16 +0200134 /* Block environment access if loaded using JTAG */
135 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
136 (op != ENVOP_INIT))
137 return ENVL_UNKNOWN;
138
139 if (prio)
140 return ENVL_UNKNOWN;
141
142 return ENVL_SPI_FLASH;
143}