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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Jon Loeliger39aa1a72008-08-26 15:01:36 -05002/*
3 * Copyright 2008 Freescale Semiconductor, Inc.
Jon Loeliger39aa1a72008-08-26 15:01:36 -05004 */
5
6#include <common.h>
Jon Loeliger39aa1a72008-08-26 15:01:36 -05007
York Sun5614e712013-09-30 09:22:09 -07008#include <fsl_ddr_sdram.h>
9#include <fsl_ddr_dimm_params.h>
Jon Loeliger39aa1a72008-08-26 15:01:36 -050010
Haiying Wangdfb49102008-10-03 12:36:55 -040011void fsl_ddr_board_options(memctl_options_t *popts,
12 dimm_params_t *pdimm,
13 unsigned int ctrl_num)
Jon Loeliger39aa1a72008-08-26 15:01:36 -050014{
15 /*
16 * Factors to consider for clock adjust:
17 * - number of chips on bus
18 * - position of slot
19 * - DDR1 vs. DDR2?
20 * - ???
21 *
22 * This needs to be determined on a board-by-board basis.
23 * 0110 3/4 cycle late
24 * 0111 7/8 cycle late
25 */
26 popts->clk_adjust = 7;
27
28 /*
29 * Factors to consider for CPO:
30 * - frequency
31 * - ddr1 vs. ddr2
32 */
33 popts->cpo_override = 10;
34
35 /*
36 * Factors to consider for write data delay:
37 * - number of DIMMs
38 *
39 * 1 = 1/4 clock delay
40 * 2 = 1/2 clock delay
41 * 3 = 3/4 clock delay
42 * 4 = 1 clock delay
43 * 5 = 5/4 clock delay
44 * 6 = 3/2 clock delay
45 */
46 popts->write_data_delay = 3;
47
Dave Liub4983e12008-11-21 16:31:43 +080048 /* 2T timing enable */
Priyanka Jain0dd38a32013-09-25 10:41:19 +053049 popts->twot_en = 1;
Dave Liub4983e12008-11-21 16:31:43 +080050
Jon Loeliger39aa1a72008-08-26 15:01:36 -050051 /*
52 * Factors to consider for half-strength driver enable:
53 * - number of DIMMs installed
54 */
55 popts->half_strength_driver_enable = 0;
56}