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Wolfgang Denkdc17fb62005-08-03 22:32:02 +02001/*
2 * (C) Copyright 2004
3 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31#define CONFIG_MPC8220 1
32#define CONFIG_YUKON8220 1 /* ... on Yukon board */
33
Becky Bruce31d82672008-05-08 19:02:12 -050034#define CONFIG_HIGH_BATS 1 /* High BATs supported */
35
Wolfgang Denkdc17fb62005-08-03 22:32:02 +020036/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
37 determine the CPU speed. */
38#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */
39#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
40
41#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
42#define BOOTFLAG_WARM 0x02 /* Software reboot */
43
Wolfgang Denkdc17fb62005-08-03 22:32:02 +020044/*
45 * Serial console configuration
46 */
47
48/* Define this for PSC console
49#define CONFIG_PSC_CONSOLE 1
50*/
51
52#define CONFIG_EXTUART_CONSOLE 1
53
54#ifdef CONFIG_EXTUART_CONSOLE
55# define CONFIG_CONS_INDEX 1
56# define CFG_NS16550_SERIAL
57# define CFG_NS16550
58# define CFG_NS16550_REG_SIZE 1
59# define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008)
60# define CFG_NS16550_CLK 18432000
61#endif
62
63#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
64
65#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
66
67#define CONFIG_TIMESTAMP /* Print image info with timestamp */
68
Jon Loeligera5562902007-07-08 15:31:57 -050069
Wolfgang Denkdc17fb62005-08-03 22:32:02 +020070/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050071 * BOOTP options
72 */
73#define CONFIG_BOOTP_BOOTFILESIZE
74#define CONFIG_BOOTP_BOOTPATH
75#define CONFIG_BOOTP_GATEWAY
76#define CONFIG_BOOTP_HOSTNAME
77
78
79/*
Jon Loeligera5562902007-07-08 15:31:57 -050080 * Command line configuration.
Wolfgang Denkdc17fb62005-08-03 22:32:02 +020081 */
Jon Loeligera5562902007-07-08 15:31:57 -050082#include <config_cmd_default.h>
83
84#define CONFIG_CMD_BOOTD
85#define CONFIG_CMD_CACHE
86#define CONFIG_CMD_DHCP
87#define CONFIG_CMD_DIAG
88#define CONFIG_CMD_EEPROM
89#define CONFIG_CMD_ELF
90#define CONFIG_CMD_I2C
91#define CONFIG_CMD_NET
92#define CONFIG_CMD_NFS
93#define CONFIG_CMD_PCI
94#define CONFIG_CMD_PING
95#define CONFIG_CMD_REGINFO
96#define CONFIG_CMD_SDRAM
97#define CONFIG_CMD_SNTP
98
Wolfgang Denkdc17fb62005-08-03 22:32:02 +020099
100#define CONFIG_NET_MULTI
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200101#define CONFIG_MII
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200102
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200103/*
104 * Autobooting
105 */
106#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
107#define CONFIG_BOOTARGS "root=/dev/ram rw"
108#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
109#define CONFIG_HAS_ETH1
110#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
111#define CONFIG_IPADDR 192.162.1.2
112#define CONFIG_NETMASK 255.255.255.0
113#define CONFIG_SERVERIP 192.162.1.1
114#define CONFIG_GATEWAYIP 192.162.1.1
115#define CONFIG_HOSTNAME yukon
116#define CONFIG_OVERWRITE_ETHADDR_ONCE
117
118
119/*
120 * I2C configuration
121 */
122#define CONFIG_HARD_I2C 1
123#define CFG_I2C_MODULE 1
124
125#define CFG_I2C_SPEED 100000 /* 100 kHz */
126#define CFG_I2C_SLAVE 0x7F
127
128/*
129 * EEPROM configuration
130 */
131#define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
132#define CFG_I2C_EEPROM_ADDR_LEN 1
133#define CFG_EEPROM_PAGE_WRITE_BITS 3
134#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
135/*
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200136#define CONFIG_ENV_IS_IN_EEPROM 1
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200137#define CFG_ENV_OFFSET 0
138#define CFG_ENV_SIZE 256
139*/
140
141/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
142 else undefined it will boot from Intel Strata flash */
143#define CFG_AMD_BOOT 1
144
145/*
146 * Flexbus Chipselect configuration
147 */
148#if defined (CFG_AMD_BOOT)
149#define CFG_CS0_BASE 0xfff0
150#define CFG_CS0_MASK 0x00080000 /* 512 KB */
151#define CFG_CS0_CTRL 0x003f0d40
152
153#define CFG_CS1_BASE 0xfe00
154#define CFG_CS1_MASK 0x01000000 /* 16 MB */
155#define CFG_CS1_CTRL 0x003f1540
156#else
157#define CFG_CS0_BASE 0xff00
158#define CFG_CS0_MASK 0x01000000 /* 16 MB */
159#define CFG_CS0_CTRL 0x003f1540
160
161#define CFG_CS1_BASE 0xfe08
162#define CFG_CS1_MASK 0x00080000 /* 512 KB */
163#define CFG_CS1_CTRL 0x003f0d40
164#endif
165
166#define CFG_CS2_BASE 0xf100
167#define CFG_CS2_MASK 0x00040000
168#define CFG_CS2_CTRL 0x003f1140
169
170#define CFG_CS3_BASE 0xf200
171#define CFG_CS3_MASK 0x00040000
172#define CFG_CS3_CTRL 0x003f1100
173
174
175#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
176#define CFG_FLASH1_BASE (CFG_CS1_BASE << 16)
177
178#if defined (CFG_AMD_BOOT)
179#define CFG_AMD_BASE CFG_FLASH0_BASE
180#define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000
181#define CFG_FLASH_BASE CFG_AMD_BASE
182#else
183#define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000
184#define CFG_AMD_BASE CFG_FLASH1_BASE
185#define CFG_FLASH_BASE CFG_INTEL_BASE
186#endif
187
188#define CFG_CPLD_BASE (CFG_CS2_BASE << 16)
189#define CFG_FPGA_BASE (CFG_CS3_BASE << 16)
190
191
192#define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */
193#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
194
195#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
196#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
197#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
198#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
199#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
200
201#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
202#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
203
204#define CFG_FLASH_CHECKSUM
205/*
206 * Environment settings
207 */
208#define CFG_ENV_IS_IN_FLASH 1
209#if defined (CFG_AMD_BOOT)
210#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
211#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE
212#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
213#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
214#define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
215#define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
216#else
217#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
218#define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE
219#define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
220#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
221#define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE
222#define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
223#endif
224
225#define CONFIG_ENV_OVERWRITE 1
226
227#if defined CFG_ENV_IS_IN_FLASH
228#undef CFG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200229#undef CONFIG_ENV_IS_IN_EEPROM
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200230#elif defined CFG_ENV_IS_IN_NVRAM
231#undef CFG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200232#undef CONFIG_ENV_IS_IN_EEPROM
233#elif defined CONFIG_ENV_IS_IN_EEPROM
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200234#undef CFG_ENV_IS_IN_NVRAM
235#undef CFG_ENV_IS_IN_FLASH
236#endif
237
238#ifndef CFG_JFFS2_FIRST_SECTOR
239#define CFG_JFFS2_FIRST_SECTOR 0
240#endif
241#ifndef CFG_JFFS2_FIRST_BANK
242#define CFG_JFFS2_FIRST_BANK 0
243#endif
244#ifndef CFG_JFFS2_NUM_BANKS
245#define CFG_JFFS2_NUM_BANKS 1
246#endif
247#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
248
249/*
250 * Memory map
251 */
252#define CFG_MBAR 0xF0000000
253#define CFG_SDRAM_BASE 0x00000000
254#define CFG_DEFAULT_MBAR 0x80000000
255#define CFG_SRAM_BASE (CFG_MBAR + 0x20000)
256#define CFG_SRAM_SIZE 0x8000
257
258/* Use SRAM until RAM will be available */
259#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000)
260#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
261
262#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
263#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
264#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
265
266#define CFG_MONITOR_BASE TEXT_BASE
267#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
268# define CFG_RAMBOOT 1
269#endif
270
271#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
272#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
273#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
274
275/* SDRAM configuration */
276#define CFG_SDRAM_TOTAL_BANKS 2
277#define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
278#define CFG_SDRAM_SPD_SIZE 0x40
279#define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
280
281/* SDRAM drive strength register */
282#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
283 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
284 (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
285 (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
286 (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
287
288/*
289 * Ethernet configuration
290 */
291#define CONFIG_MPC8220_FEC 1
292#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
293#define CONFIG_PHY_ADDR 0x18
294
295
296/*
297 * Miscellaneous configurable options
298 */
299#define CFG_LONGHELP /* undef to save memory */
300#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligera5562902007-07-08 15:31:57 -0500301#if defined(CONFIG_CMD_KGDB)
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200302#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
303#else
304#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
305#endif
306#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
307#define CFG_MAXARGS 16 /* max number of command args */
308#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
309
310#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
311#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
312
313#define CFG_LOAD_ADDR 0x100000 /* default load address */
314
315#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
316
Jon Loeligera5562902007-07-08 15:31:57 -0500317#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
318#if defined(CONFIG_CMD_KGDB)
319# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
320#endif
321
Wolfgang Denkdc17fb62005-08-03 22:32:02 +0200322/*
323 * Various low-level settings
324 */
325#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
326#define CFG_HID0_FINAL HID0_ICE
327
328#endif /* __CONFIG_H */