blob: c4aca08f0df3aeb6e00fbf9be0b3f5de08852565 [file] [log] [blame]
Simon Glass8ef07572014-11-12 22:42:07 -07001/*
2 * Copyright (c) 2014 Google, Inc
3 * (C) Copyright 2008
4 * Graeme Russ, graeme.russ@gmail.com.
5 *
6 * Some portions from coreboot src/mainboard/google/link/romstage.c
Simon Glass8e0df062014-11-12 22:42:23 -07007 * and src/cpu/intel/model_206ax/bootblock.c
Simon Glass8ef07572014-11-12 22:42:07 -07008 * Copyright (C) 2007-2010 coresystems GmbH
9 * Copyright (C) 2011 Google Inc.
10 *
11 * SPDX-License-Identifier: GPL-2.0
12 */
13
14#include <common.h>
Simon Glassaad78d22015-03-05 12:25:33 -070015#include <dm.h>
Simon Glass2b605152014-11-12 22:42:15 -070016#include <errno.h>
17#include <fdtdec.h>
Simon Glass858361b2016-01-17 16:11:13 -070018#include <pch.h>
Simon Glass8ef07572014-11-12 22:42:07 -070019#include <asm/cpu.h>
Simon Glass50dd3da2016-03-11 22:06:58 -070020#include <asm/cpu_common.h>
Simon Glass06d336c2016-03-11 22:06:55 -070021#include <asm/intel_regs.h>
Simon Glassf5fbbe92014-11-12 22:42:19 -070022#include <asm/io.h>
Simon Glass3eafce02014-11-12 22:42:27 -070023#include <asm/lapic.h>
Simon Glass7e4a6ae2016-03-16 07:44:36 -060024#include <asm/lpc_common.h>
Simon Glass9e665062016-03-11 22:06:54 -070025#include <asm/microcode.h>
Simon Glassf5fbbe92014-11-12 22:42:19 -070026#include <asm/msr.h>
27#include <asm/mtrr.h>
Simon Glass6e5b12b2014-11-12 22:42:13 -070028#include <asm/pci.h>
Simon Glass70a09c62014-11-12 22:42:10 -070029#include <asm/post.h>
Simon Glass8ef07572014-11-12 22:42:07 -070030#include <asm/processor.h>
Simon Glassf5fbbe92014-11-12 22:42:19 -070031#include <asm/arch/model_206ax.h>
Simon Glass2b605152014-11-12 22:42:15 -070032#include <asm/arch/pch.h>
Simon Glass8e0df062014-11-12 22:42:23 -070033#include <asm/arch/sandybridge.h>
Simon Glass8ef07572014-11-12 22:42:07 -070034
35DECLARE_GLOBAL_DATA_PTR;
36
Simon Glassf5fbbe92014-11-12 22:42:19 -070037static int set_flex_ratio_to_tdp_nominal(void)
38{
Simon Glassf5fbbe92014-11-12 22:42:19 -070039 /* Minimum CPU revision for configurable TDP support */
40 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
41 return -EINVAL;
42
Simon Glass50dd3da2016-03-11 22:06:58 -070043 return cpu_set_flex_ratio_to_tdp_nominal();
Simon Glassf5fbbe92014-11-12 22:42:19 -070044}
45
Simon Glass8ef07572014-11-12 22:42:07 -070046int arch_cpu_init(void)
47{
Simon Glass161d2e42015-03-05 12:25:17 -070048 post_code(POST_CPU_INIT);
Simon Glass161d2e42015-03-05 12:25:17 -070049
50 return x86_cpu_init_f();
51}
52
53int arch_cpu_init_dm(void)
54{
Simon Glass6e5b12b2014-11-12 22:42:13 -070055 struct pci_controller *hose;
Simon Glass4acc83d2016-01-17 16:11:10 -070056 struct udevice *bus, *dev;
Simon Glass8ef07572014-11-12 22:42:07 -070057 int ret;
58
Simon Glassaad78d22015-03-05 12:25:33 -070059 post_code(0x70);
60 ret = uclass_get_device(UCLASS_PCI, 0, &bus);
61 post_code(0x71);
Simon Glass8ef07572014-11-12 22:42:07 -070062 if (ret)
63 return ret;
Simon Glassaad78d22015-03-05 12:25:33 -070064 post_code(0x72);
65 hose = dev_get_uclass_priv(bus);
Simon Glass8ef07572014-11-12 22:42:07 -070066
Simon Glassaad78d22015-03-05 12:25:33 -070067 /* TODO(sjg@chromium.org): Get rid of gd->hose */
68 gd->hose = hose;
Simon Glass6e5b12b2014-11-12 22:42:13 -070069
Simon Glass3f603cb2016-02-11 13:23:26 -070070 ret = uclass_first_device_err(UCLASS_LPC, &dev);
71 if (ret)
72 return ret;
Simon Glass4acc83d2016-01-17 16:11:10 -070073
Simon Glassf5fbbe92014-11-12 22:42:19 -070074 /*
75 * We should do as little as possible before the serial console is
76 * up. Perhaps this should move to later. Our next lot of init
77 * happens in print_cpuinfo() when we have a console
78 */
79 ret = set_flex_ratio_to_tdp_nominal();
80 if (ret)
81 return ret;
82
Simon Glass8ef07572014-11-12 22:42:07 -070083 return 0;
84}
85
Simon Glass8e0df062014-11-12 22:42:23 -070086#define PCH_EHCI0_TEMP_BAR0 0xe8000000
87#define PCH_EHCI1_TEMP_BAR0 0xe8000400
88#define PCH_XHCI_TEMP_BAR0 0xe8001000
89
90/*
91 * Setup USB controller MMIO BAR to prevent the reference code from
92 * resetting the controller.
93 *
94 * The BAR will be re-assigned during device enumeration so these are only
95 * temporary.
96 *
97 * This is used to speed up the resume path.
98 */
Simon Glass5213f282016-01-17 16:11:46 -070099static void enable_usb_bar(struct udevice *bus)
Simon Glass8e0df062014-11-12 22:42:23 -0700100{
101 pci_dev_t usb0 = PCH_EHCI1_DEV;
102 pci_dev_t usb1 = PCH_EHCI2_DEV;
103 pci_dev_t usb3 = PCH_XHCI_DEV;
Simon Glass5213f282016-01-17 16:11:46 -0700104 ulong cmd;
Simon Glass8e0df062014-11-12 22:42:23 -0700105
106 /* USB Controller 1 */
Simon Glass5213f282016-01-17 16:11:46 -0700107 pci_bus_write_config(bus, usb0, PCI_BASE_ADDRESS_0,
108 PCH_EHCI0_TEMP_BAR0, PCI_SIZE_32);
109 pci_bus_read_config(bus, usb0, PCI_COMMAND, &cmd, PCI_SIZE_32);
Simon Glass8e0df062014-11-12 22:42:23 -0700110 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
Simon Glass5213f282016-01-17 16:11:46 -0700111 pci_bus_write_config(bus, usb0, PCI_COMMAND, cmd, PCI_SIZE_32);
Simon Glass8e0df062014-11-12 22:42:23 -0700112
Simon Glass5213f282016-01-17 16:11:46 -0700113 /* USB Controller 2 */
114 pci_bus_write_config(bus, usb1, PCI_BASE_ADDRESS_0,
115 PCH_EHCI1_TEMP_BAR0, PCI_SIZE_32);
116 pci_bus_read_config(bus, usb1, PCI_COMMAND, &cmd, PCI_SIZE_32);
Simon Glass8e0df062014-11-12 22:42:23 -0700117 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
Simon Glass5213f282016-01-17 16:11:46 -0700118 pci_bus_write_config(bus, usb1, PCI_COMMAND, cmd, PCI_SIZE_32);
Simon Glass8e0df062014-11-12 22:42:23 -0700119
Simon Glass5213f282016-01-17 16:11:46 -0700120 /* USB3 Controller 1 */
121 pci_bus_write_config(bus, usb3, PCI_BASE_ADDRESS_0,
122 PCH_XHCI_TEMP_BAR0, PCI_SIZE_32);
123 pci_bus_read_config(bus, usb3, PCI_COMMAND, &cmd, PCI_SIZE_32);
Simon Glass8e0df062014-11-12 22:42:23 -0700124 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
Simon Glass5213f282016-01-17 16:11:46 -0700125 pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
Simon Glass8e0df062014-11-12 22:42:23 -0700126}
127
Simon Glass8ef07572014-11-12 22:42:07 -0700128int print_cpuinfo(void)
129{
Simon Glass8e0df062014-11-12 22:42:23 -0700130 enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
Simon Glass8ef07572014-11-12 22:42:07 -0700131 char processor_name[CPU_MAX_NAME_LEN];
Simon Glassf633efa2016-01-17 16:11:19 -0700132 struct udevice *dev, *lpc;
Simon Glass8ef07572014-11-12 22:42:07 -0700133 const char *name;
Simon Glass8e0df062014-11-12 22:42:23 -0700134 uint32_t pm1_cnt;
135 uint16_t pm1_sts;
Simon Glass94060ff2014-11-12 22:42:20 -0700136 int ret;
137
Simon Glass8e0df062014-11-12 22:42:23 -0700138 /* TODO: cmos_post_init() */
139 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
140 debug("soft reset detected\n");
141 boot_mode = PEI_BOOT_SOFT_RESET;
142
143 /* System is not happy after keyboard reset... */
144 debug("Issuing CF9 warm reset\n");
Simon Glass5021c812015-04-28 20:11:30 -0600145 reset_cpu(0);
Simon Glass8e0df062014-11-12 22:42:23 -0700146 }
147
Simon Glass50dd3da2016-03-11 22:06:58 -0700148 ret = cpu_common_init();
Simon Glass4cc00f02016-07-25 18:58:59 -0600149 if (ret) {
150 debug("%s: cpu_common_init() failed\n", __func__);
Simon Glass858361b2016-01-17 16:11:13 -0700151 return ret;
Simon Glass4cc00f02016-07-25 18:58:59 -0600152 }
Simon Glass8e0df062014-11-12 22:42:23 -0700153
154 /* Check PM1_STS[15] to see if we are waking from Sx */
155 pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
156
157 /* Read PM1_CNT[12:10] to determine which Sx state */
158 pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
159
160 if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
Simon Glass8e0df062014-11-12 22:42:23 -0700161 debug("Resume from S3 detected, but disabled.\n");
Simon Glass8e0df062014-11-12 22:42:23 -0700162 } else {
163 /*
164 * TODO: An indication of life might be possible here (e.g.
165 * keyboard light)
166 */
167 }
168 post_code(POST_EARLY_INIT);
169
170 /* Enable SPD ROMs and DDR-III DRAM */
Simon Glass3f603cb2016-02-11 13:23:26 -0700171 ret = uclass_first_device_err(UCLASS_I2C, &dev);
Simon Glass8d8f3ac2017-01-16 07:03:38 -0700172 if (ret) {
173 debug("%s: Failed to get I2C (ret=%d)\n", __func__, ret);
Simon Glass8e0df062014-11-12 22:42:23 -0700174 return ret;
Simon Glass8d8f3ac2017-01-16 07:03:38 -0700175 }
Simon Glass8e0df062014-11-12 22:42:23 -0700176
177 /* Prepare USB controller early in S3 resume */
Simon Glass50dd3da2016-03-11 22:06:58 -0700178 if (boot_mode == PEI_BOOT_RESUME) {
179 uclass_first_device(UCLASS_LPC, &lpc);
Simon Glass5213f282016-01-17 16:11:46 -0700180 enable_usb_bar(pci_get_controller(lpc->parent));
Simon Glass50dd3da2016-03-11 22:06:58 -0700181 }
Simon Glass8e0df062014-11-12 22:42:23 -0700182
183 gd->arch.pei_boot_mode = boot_mode;
184
Simon Glass8ef07572014-11-12 22:42:07 -0700185 /* Print processor name */
186 name = cpu_get_name(processor_name);
187 printf("CPU: %s\n", name);
188
Simon Glass8e0df062014-11-12 22:42:23 -0700189 post_code(POST_CPU_INFO);
190
Simon Glass8ef07572014-11-12 22:42:07 -0700191 return 0;
192}
Simon Glass7b952522015-10-18 19:51:27 -0600193
194void board_debug_uart_init(void)
195{
196 /* This enables the debug UART */
197 pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN,
198 PCI_SIZE_16);
199}