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Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +00001/*
2 * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __CONFIG_IGEP0033_H
15#define __CONFIG_IGEP0033_H
16
17#define CONFIG_AM33XX
SRICHARAN R4a0eb752013-04-24 00:41:24 +000018#define CONFIG_OMAP
Lokesh Vutla806d2792013-07-30 11:36:30 +053019#define CONFIG_OMAP_COMMON
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000020
21#include <asm/arch/omap.h>
22
23/* Mach type */
24#define MACH_TYPE_IGEP0033 4521 /* Until the next sync */
25#define CONFIG_MACH_TYPE MACH_TYPE_IGEP0033
26
27/* Clock defines */
28#define V_OSCK 24000000 /* Clock output from T2 */
29#define V_SCLK (V_OSCK)
30
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000031#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
32#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
33#define CONFIG_SYS_LONGHELP /* undef to save memory */
34#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
35#define CONFIG_SYS_PROMPT "U-Boot# "
36#define CONFIG_SYS_NO_FLASH
37
38/* Display cpuinfo */
39#define CONFIG_DISPLAY_CPUINFO
40
Enric Balletbò i Serra2e6bc672013-07-25 09:27:37 +020041/* Flattened Device Tree */
42#define CONFIG_OF_LIBFDT
43
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000044/* Commands to include */
45#include <config_cmd_default.h>
46
47#define CONFIG_CMD_ASKENV
48#define CONFIG_CMD_BOOTZ
49#define CONFIG_CMD_DHCP
50#define CONFIG_CMD_ECHO
51#define CONFIG_CMD_EXT4
52#define CONFIG_CMD_FAT
53#define CONFIG_CMD_FS_GENERIC
54#define CONFIG_CMD_MMC
55#define CONFIG_CMD_MTDPARTS
56#define CONFIG_CMD_NAND
57#define CONFIG_CMD_NET
58#define CONFIG_CMD_PING
59#define CONFIG_CMD_UBI
60#define CONFIG_CMD_UBIFS
61
Enric Balletbo i Serracf8d0052013-07-25 09:27:39 +020062/* Make the verbose messages from UBI stop printing */
63#define CONFIG_UBI_SILENCE_MSG
64#define CONFIG_UBIFS_SILENCE_MSG
65
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000066#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */
67#define CONFIG_ENV_VARS_UBOOT_CONFIG
68#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
69#define CONFIG_EXTRA_ENV_SETTINGS \
Enric Balletbò i Serra2e6bc672013-07-25 09:27:37 +020070 "loadaddr=0x80F80000\0" \
71 "dtbaddr=0x80200000\0" \
72 "bootdir=/boot\0" \
73 "bootfile=zImage\0" \
74 "dtbfile=am335x-base0033.dtb\0" \
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000075 "console=ttyO0,115200n8\0" \
Enric Balletbo i Serracf8d0052013-07-25 09:27:39 +020076 "mtdids=" MTDIDS_DEFAULT "\0" \
77 "mtdparts=" MTDPARTS_DEFAULT "\0" \
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000078 "mmcdev=0\0" \
79 "mmcroot=/dev/mmcblk0p2 rw\0" \
Enric Balletbo i Serracf8d0052013-07-25 09:27:39 +020080 "ubiroot=ubi0:filesystem rw ubi.mtd=3,2048\0" \
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000081 "mmcrootfstype=ext4 rootwait\0" \
Enric Balletbo i Serracf8d0052013-07-25 09:27:39 +020082 "ubirootfstype=ubifs rootwait\0" \
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000083 "mmcargs=setenv bootargs console=${console} " \
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000084 "root=${mmcroot} " \
85 "rootfstype=${mmcrootfstype}\0" \
Enric Balletbo i Serracf8d0052013-07-25 09:27:39 +020086 "ubiargs=setenv bootargs console=${console} " \
87 "root=${ubiroot} " \
88 "rootfstype=${ubirootfstype}\0" \
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000089 "bootenv=uEnv.txt\0" \
90 "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
91 "importbootenv=echo Importing environment from mmc ...; " \
Enric Balletbò i Serra2e6bc672013-07-25 09:27:37 +020092 "env import -t ${loadaddr} ${filesize}\0" \
93 "mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
94 "load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
Enric Balletbo i Serracf8d0052013-07-25 09:27:39 +020095 "ubiload=ubi part filesystem 2048; ubifsmount ubi0; " \
96 "ubifsload ${loadaddr} ${bootdir}/${bootfile}; " \
97 "ubifsload ${dtbaddr} ${bootdir}/${dtbfile} \0" \
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +000098 "mmcboot=echo Booting from mmc ...; " \
99 "run mmcargs; " \
Enric Balletbò i Serra2e6bc672013-07-25 09:27:37 +0200100 "bootz ${loadaddr} - ${dtbaddr}\0" \
Enric Balletbo i Serracf8d0052013-07-25 09:27:39 +0200101 "ubiboot=echo Booting from nand (ubifs) ...; " \
102 "run ubiargs; run ubiload; " \
103 "bootz ${loadaddr} - ${dtbaddr}\0" \
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000104
105#define CONFIG_BOOTCOMMAND \
106 "mmc dev ${mmcdev}; if mmc rescan; then " \
107 "echo SD/MMC found on device ${mmcdev};" \
108 "if run loadbootenv; then " \
109 "echo Loaded environment from ${bootenv};" \
110 "run importbootenv;" \
111 "fi;" \
112 "if test -n $uenvcmd; then " \
113 "echo Running uenvcmd ...;" \
114 "run uenvcmd;" \
115 "fi;" \
Enric Balletbò i Serra2e6bc672013-07-25 09:27:37 +0200116 "if run mmcload; then " \
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000117 "run mmcboot;" \
118 "fi;" \
Enric Balletbo i Serracf8d0052013-07-25 09:27:39 +0200119 "else " \
120 "run ubiboot;" \
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000121 "fi;" \
122
123/* Max number of command args */
124#define CONFIG_SYS_MAXARGS 16
125
126/* Console I/O Buffer Size */
127#define CONFIG_SYS_CBSIZE 512
128
129/* Print Buffer Size */
130#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
131 + sizeof(CONFIG_SYS_PROMPT) + 16)
132
133/* Boot Argument Buffer Size */
134#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
135#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000136
137/* Physical Memory Map */
138#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000139#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
140
Tom Rini73feefd2013-08-09 11:22:13 -0400141#define CONFIG_SYS_SDRAM_BASE 0x80000000
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000142#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
143 GENERATED_GBL_DATA_SIZE)
144/* Platform/Board specific defs */
145#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
146#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000147
148/* NS16550 Configuration */
149#define CONFIG_SYS_NS16550
150#define CONFIG_SYS_NS16550_SERIAL
151#define CONFIG_SYS_NS16550_REG_SIZE (-4)
152#define CONFIG_SYS_NS16550_CLK (48000000)
153#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
154
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000155#define CONFIG_CONS_INDEX 1
156#define CONFIG_BAUDRATE 115200
157
SRICHARAN R47c6ea02013-04-24 00:41:25 +0000158/* CPU */
159#define CONFIG_ARCH_CPU_INIT
160
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000161#define CONFIG_ENV_OVERWRITE 1
162#define CONFIG_SYS_CONSOLE_INFO_QUIET
163
164/* MMC support */
165#define CONFIG_MMC
166#define CONFIG_GENERIC_MMC
167#define CONFIG_OMAP_HSMMC
168#define CONFIG_DOS_PARTITION
169
170/* GPIO support */
171#define CONFIG_OMAP_GPIO
172
173/* Ethernet support */
174#define CONFIG_DRIVER_TI_CPSW
175#define CONFIG_MII
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000176#define CONFIG_BOOTP_DNS
177#define CONFIG_BOOTP_DNS2
178#define CONFIG_BOOTP_SEND_HOSTNAME
179#define CONFIG_BOOTP_GATEWAY
180#define CONFIG_BOOTP_SUBNETMASK
181#define CONFIG_NET_RETRY_COUNT 10
182#define CONFIG_NET_MULTI
183#define CONFIG_PHYLIB
184#define CONFIG_PHY_ADDR 0
185#define CONFIG_PHY_SMSC
186
187/* NAND support */
188#define CONFIG_NAND
189#define CONFIG_NAND_OMAP_GPMC
pekon guptabeba5f02013-11-18 19:02:59 +0530190#define CONFIG_NAND_OMAP_ELM
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000191#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
192#define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */
193#define CONFIG_SYS_MAX_NAND_DEVICE 1
194#define CONFIG_SYS_NAND_ONFI_DETECTION 1
195#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
Enric Balletbo i Serracf8d0052013-07-25 09:27:39 +0200196#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000197#define CONFIG_ENV_IS_IN_NAND
Enric Balletbo i Serracf8d0052013-07-25 09:27:39 +0200198#define CONFIG_ENV_OFFSET 0x180000 /* environment starts here */
199#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_OFFSET + CONFIG_SYS_ENV_SECT_SIZE)
200#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000201
202#define CONFIG_MTD_PARTITIONS
203#define CONFIG_MTD_DEVICE
204#define CONFIG_RBTREE
205#define CONFIG_LZO
206
Enric Balletbo i Serracf8d0052013-07-25 09:27:39 +0200207#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
208#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(spl),"\
209 "1m(uboot),256k(environment),"\
210 "-(filesystem)"
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000211
212/* Unsupported features */
213#undef CONFIG_USE_IRQ
214
215/* Defines for SPL */
216#define CONFIG_SPL
217#define CONFIG_SPL_FRAMEWORK
Tom Rini320d9742013-05-31 10:48:03 -0400218/*
Tom Riniedfcf852013-06-06 08:57:45 -0400219 * Place the image at the start of the ROM defined image space.
Tom Rini320d9742013-05-31 10:48:03 -0400220 * We limit our size to the ROM-defined downloaded image area, and use the
221 * rest of the space for stack.
222 */
Tom Riniedfcf852013-06-06 08:57:45 -0400223#define CONFIG_SPL_TEXT_BASE 0x402F0400
Tom Rini320d9742013-05-31 10:48:03 -0400224#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE)
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000225#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
226
227#define CONFIG_SPL_BSS_START_ADDR 0x80000000
228#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
229
230#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
231#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
232#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
233#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
234#define CONFIG_SPL_MMC_SUPPORT
235#define CONFIG_SPL_FAT_SUPPORT
236#define CONFIG_SPL_LIBCOMMON_SUPPORT
237#define CONFIG_SPL_LIBDISK_SUPPORT
238#define CONFIG_SPL_LIBGENERIC_SUPPORT
239#define CONFIG_SPL_SERIAL_SUPPORT
240#define CONFIG_SPL_GPIO_SUPPORT
241#define CONFIG_SPL_YMODEM_SUPPORT
242#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
243
244#define CONFIG_SPL_BOARD_INIT
245#define CONFIG_SPL_NAND_AM33XX_BCH
246#define CONFIG_SPL_NAND_SUPPORT
247#define CONFIG_SPL_NAND_BASE
248#define CONFIG_SPL_NAND_DRIVERS
249#define CONFIG_SPL_NAND_ECC
250#define CONFIG_SYS_NAND_5_ADDR_CYCLE
251#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
252 CONFIG_SYS_NAND_PAGE_SIZE)
253#define CONFIG_SYS_NAND_PAGE_SIZE 2048
254#define CONFIG_SYS_NAND_OOBSIZE 64
255#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
256#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
257#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
258 10, 11, 12, 13, 14, 15, 16, 17, \
259 18, 19, 20, 21, 22, 23, 24, 25, \
260 26, 27, 28, 29, 30, 31, 32, 33, \
261 34, 35, 36, 37, 38, 39, 40, 41, \
262 42, 43, 44, 45, 46, 47, 48, 49, \
263 50, 51, 52, 53, 54, 55, 56, 57, }
264
265#define CONFIG_SYS_NAND_ECCSIZE 512
266#define CONFIG_SYS_NAND_ECCBYTES 14
pekon gupta3f719062013-11-18 19:03:01 +0530267#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000268
Enric Balletbo i Serra5f5c1d12013-04-04 22:27:58 +0000269#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
270
271#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
272
273/*
274 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
275 * 64 bytes before this address should be set aside for u-boot.img's
276 * header. That is 0x800FFFC0--0x80100000 should not be used for any
277 * other needs.
278 */
279#define CONFIG_SYS_TEXT_BASE 0x80800000
280#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
281#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
282
283/*
284 * Since SPL did pll and ddr initialization for us,
285 * we don't need to do it twice.
286 */
287#ifndef CONFIG_SPL_BUILD
288#define CONFIG_SKIP_LOWLEVEL_INIT
289#endif
290
291#endif /* ! __CONFIG_IGEP0033_H */