blob: b3e5c5e5e09b5db5d04bfac1b8bd3093b9d3d655 [file] [log] [blame]
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +00001/*
2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +00006 */
7
8#include <common.h>
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +00009#include <dwmmc.h>
Amara082a2d2013-04-27 11:42:55 +053010#include <fdtdec.h>
11#include <libfdt.h>
12#include <malloc.h>
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000013#include <asm/arch/dwmmc.h>
14#include <asm/arch/clk.h>
Amara082a2d2013-04-27 11:42:55 +053015#include <asm/arch/pinmux.h>
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000016
Amara082a2d2013-04-27 11:42:55 +053017#define DWMMC_MAX_CH_NUM 4
18#define DWMMC_MAX_FREQ 52000000
19#define DWMMC_MIN_FREQ 400000
20#define DWMMC_MMC0_CLKSEL_VAL 0x03030001
21#define DWMMC_MMC2_CLKSEL_VAL 0x03020001
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000022
Amara082a2d2013-04-27 11:42:55 +053023/*
24 * Function used as callback function to initialise the
25 * CLKSEL register for every mmc channel.
26 */
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000027static void exynos_dwmci_clksel(struct dwmci_host *host)
28{
Amara082a2d2013-04-27 11:42:55 +053029 dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000030}
31
Amara082a2d2013-04-27 11:42:55 +053032unsigned int exynos_dwmci_get_clk(int dev_index)
33{
34 return get_mmc_clk(dev_index);
35}
36
Jaehoon Chung18ab6752013-11-29 20:08:57 +090037static void exynos_dwmci_board_init(struct dwmci_host *host)
38{
39 if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
40 dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
41 dwmci_writel(host, EMMCP_SEND0, 0);
42 dwmci_writel(host, EMMCP_CTRL0,
43 MPSCTRL_SECURE_READ_BIT |
44 MPSCTRL_SECURE_WRITE_BIT |
45 MPSCTRL_NON_SECURE_READ_BIT |
46 MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
47 }
48}
49
Amara082a2d2013-04-27 11:42:55 +053050/*
51 * This function adds the mmc channel to be registered with mmc core.
52 * index - mmc channel number.
53 * regbase - register base address of mmc channel specified in 'index'.
54 * bus_width - operating bus width of mmc channel specified in 'index'.
55 * clksel - value to be written into CLKSEL register in case of FDT.
56 * NULL in case od non-FDT.
57 */
58int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000059{
60 struct dwmci_host *host = NULL;
Amara082a2d2013-04-27 11:42:55 +053061 unsigned int div;
62 unsigned long freq, sclk;
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000063 host = malloc(sizeof(struct dwmci_host));
64 if (!host) {
65 printf("dwmci_host malloc fail!\n");
66 return 1;
67 }
Amara082a2d2013-04-27 11:42:55 +053068 /* request mmc clock vlaue of 52MHz. */
69 freq = 52000000;
70 sclk = get_mmc_clk(index);
71 div = DIV_ROUND_UP(sclk, freq);
72 /* set the clock divisor for mmc */
73 set_mmc_clk(index, div);
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000074
Amara082a2d2013-04-27 11:42:55 +053075 host->name = "EXYNOS DWMMC";
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000076 host->ioaddr = (void *)regbase;
77 host->buswidth = bus_width;
Rajeshwari Shinde6f0b7ca2013-10-29 12:53:13 +053078#ifdef CONFIG_EXYNOS5420
79 host->quirks = DWMCI_QUIRK_DISABLE_SMU;
80#endif
Jaehoon Chung18ab6752013-11-29 20:08:57 +090081 host->board_init = exynos_dwmci_board_init;
Amara082a2d2013-04-27 11:42:55 +053082
83 if (clksel) {
84 host->clksel_val = clksel;
85 } else {
86 if (0 == index)
87 host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
88 if (2 == index)
89 host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
90 }
91
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000092 host->clksel = exynos_dwmci_clksel;
93 host->dev_index = index;
Jaehoon Chungb44fe832013-10-06 18:59:31 +090094 host->get_mmc_clk = exynos_dwmci_get_clk;
Amara082a2d2013-04-27 11:42:55 +053095 /* Add the mmc channel to be registered with mmc core */
96 if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
97 debug("dwmmc%d registration failed\n", index);
98 return -1;
99 }
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +0000100 return 0;
101}
102
Amara082a2d2013-04-27 11:42:55 +0530103#ifdef CONFIG_OF_CONTROL
104int exynos_dwmmc_init(const void *blob)
105{
106 int index, bus_width;
107 int node_list[DWMMC_MAX_CH_NUM];
108 int err = 0, dev_id, flag, count, i;
109 u32 clksel_val, base, timing[3];
110
111 count = fdtdec_find_aliases_for_id(blob, "mmc",
112 COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
113 DWMMC_MAX_CH_NUM);
114
115 for (i = 0; i < count; i++) {
116 int node = node_list[i];
117
118 if (node <= 0)
119 continue;
120
121 /* Extract device id for each mmc channel */
122 dev_id = pinmux_decode_periph_id(blob, node);
123
124 /* Get the bus width from the device node */
125 bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
126 if (bus_width <= 0) {
127 debug("DWMMC: Can't get bus-width\n");
128 return -1;
129 }
130 if (8 == bus_width)
131 flag = PINMUX_FLAG_8BIT_MODE;
132 else
133 flag = PINMUX_FLAG_NONE;
134
135 /* config pinmux for each mmc channel */
136 err = exynos_pinmux_config(dev_id, flag);
137 if (err) {
138 debug("DWMMC not configured\n");
139 return err;
140 }
141
142 index = dev_id - PERIPH_ID_SDMMC0;
143
144 /* Get the base address from the device node */
145 base = fdtdec_get_addr(blob, node, "reg");
146 if (!base) {
147 debug("DWMMC: Can't get base address\n");
148 return -1;
149 }
150 /* Extract the timing info from the node */
151 err = fdtdec_get_int_array(blob, node, "samsung,timing",
152 timing, 3);
153 if (err) {
154 debug("Can't get sdr-timings for divider\n");
155 return -1;
156 }
157
158 clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
159 DWMCI_SET_DRV_CLK(timing[1]) |
160 DWMCI_SET_DIV_RATIO(timing[2]));
161 /* Initialise each mmc channel */
162 err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
163 if (err)
164 debug("dwmmc Channel-%d init failed\n", index);
165 }
166 return 0;
167}
168#endif