blob: 5e3c88ab6f244331b86e76e45d5a46757c1f1e56 [file] [log] [blame]
Aubrey Li65458982007-03-20 18:16:24 +08001#define ASSEMBLY
2
3#include <linux/config.h>
4#include <config.h>
5#include <asm/blackfin.h>
6#include <asm/mem_init.h>
7.global init_sdram;
8
9#if (CONFIG_CCLK_DIV == 1)
10#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
11#endif
12#if (CONFIG_CCLK_DIV == 2)
13#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
14#endif
15#if (CONFIG_CCLK_DIV == 4)
16#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
17#endif
18#if (CONFIG_CCLK_DIV == 8)
19#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
20#endif
21#ifndef CONFIG_CCLK_ACT_DIV
22#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
23#endif
24
25init_sdram:
26 [--SP] = ASTAT;
27 [--SP] = RETS;
28 [--SP] = (R7:0);
29 [--SP] = (P5:0);
30
31
32 p0.h = hi(SICA_IWR0);
33 p0.l = lo(SICA_IWR0);
34 r0.l = 0x1;
35 w[p0] = r0.l;
36 SSYNC;
37
38 p0.h = hi(SPI_BAUD);
39 p0.l = lo(SPI_BAUD);
40 r0.l = CONFIG_SPI_BAUD_INITBLOCK;
41 w[p0] = r0.l;
42 SSYNC;
43
44 /*
45 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
46 */
47 p0.h = hi(PLL_LOCKCNT);
48 p0.l = lo(PLL_LOCKCNT);
49 r0 = 0x300(Z);
50 w[p0] = r0.l;
51 ssync;
52
53 /*
54 * Put SDRAM in self-refresh, incase anything is running
55 */
56 P2.H = hi(EBIU_SDGCTL);
57 P2.L = lo(EBIU_SDGCTL);
58 R0 = [P2];
59 BITSET (R0, 24);
60 [P2] = R0;
61 SSYNC;
62
63 /*
64 * Set PLL_CTL with the value that we calculate in R0
65 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
66 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
67 * - [7] = output delay (add 200ps of delay to mem signals)
68 * - [6] = input delay (add 200ps of input delay to mem signals)
69 * - [5] = PDWN : 1=All Clocks off
70 * - [3] = STOPCK : 1=Core Clock off
71 * - [1] = PLL_OFF : 1=Disable Power to PLL
72 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
73 * all other bits set to zero
74 */
75
76 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
77 r0 = r0 << 9; /* Shift it over, */
78 r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */
79 r0 = r1 | r0;
80 r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
81 r1 = r1 << 8; /* Shift it over */
82 r0 = r1 | r0; /* add them all together */
83
84 p0.h = hi(PLL_CTL);
85 p0.l = lo(PLL_CTL); /* Load the address */
86 cli r2; /* Disable interrupts */
87 ssync;
88 w[p0] = r0.l; /* Set the value */
89 idle; /* Wait for the PLL to stablize */
90 sti r2; /* Enable interrupts */
91
92check_again:
93 p0.h = hi(PLL_STAT);
94 p0.l = lo(PLL_STAT);
95 R0 = W[P0](Z);
96 CC = BITTST(R0,5);
97 if ! CC jump check_again;
98
99 /* Configure SCLK & CCLK Dividers */
100 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
101 p0.h = hi(PLL_DIV);
102 p0.l = lo(PLL_DIV);
103 w[p0] = r0.l;
104 ssync;
105
106 /*
107 * We now are running at speed, time to set the Async mem bank wait states
108 * This will speed up execution, since we are normally running from FLASH.
109 */
110
111 p2.h = (EBIU_AMBCTL1 >> 16);
112 p2.l = (EBIU_AMBCTL1 & 0xFFFF);
113 r0.h = (AMBCTL1VAL >> 16);
114 r0.l = (AMBCTL1VAL & 0xFFFF);
115 [p2] = r0;
116 ssync;
117
118 p2.h = (EBIU_AMBCTL0 >> 16);
119 p2.l = (EBIU_AMBCTL0 & 0xFFFF);
120 r0.h = (AMBCTL0VAL >> 16);
121 r0.l = (AMBCTL0VAL & 0xFFFF);
122 [p2] = r0;
123 ssync;
124
125 p2.h = (EBIU_AMGCTL >> 16);
126 p2.l = (EBIU_AMGCTL & 0xffff);
127 r0 = AMGCTLVAL;
128 w[p2] = r0;
129 ssync;
130
131 /*
132 * Now, Initialize the SDRAM,
133 * start with the SDRAM Refresh Rate Control Register
134 */
135 p0.l = lo(EBIU_SDRRC);
136 p0.h = hi(EBIU_SDRRC);
137 r0 = mem_SDRRC;
138 w[p0] = r0.l;
139 ssync;
140
141 /*
142 * SDRAM Memory Bank Control Register - bank specific parameters
143 */
144 p0.l = (EBIU_SDBCTL & 0xFFFF);
145 p0.h = (EBIU_SDBCTL >> 16);
146 r0 = mem_SDBCTL;
147 w[p0] = r0.l;
148 ssync;
149
150 /*
151 * SDRAM Global Control Register - global programmable parameters
152 * Disable self-refresh
153 */
154 P2.H = hi(EBIU_SDGCTL);
155 P2.L = lo(EBIU_SDGCTL);
156 R0 = [P2];
157 BITCLR (R0, 24);
158
159 /*
160 * Check if SDRAM is already powered up, if it is, enable self-refresh
161 */
162 p0.h = hi(EBIU_SDSTAT);
163 p0.l = lo(EBIU_SDSTAT);
164 r2.l = w[p0];
165 cc = bittst(r2,3);
166 if !cc jump skip;
167 NOP;
168 BITSET (R0, 23);
169skip:
170 [P2] = R0;
171 SSYNC;
172
173 /* Write in the new value in the register */
174 R0.L = lo(mem_SDGCTL);
175 R0.H = hi(mem_SDGCTL);
176 [P2] = R0;
177 SSYNC;
178 nop;
179
180
181 (P5:0) = [SP++];
182 (R7:0) = [SP++];
183 RETS = [SP++];
184 ASTAT = [SP++];
185 RTS;