blob: 622117109280b0e976607d74161787dbbac90df9 [file] [log] [blame]
Dirk Eibacha605ea72010-10-21 10:50:05 +02001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
26#include <asm/processor.h>
27#include <asm/io.h>
28#include <asm/ppc4xx-gpio.h>
Dirk Eibach2da0fc02011-01-21 09:31:21 +010029#include <asm/global_data.h>
Dirk Eibacha605ea72010-10-21 10:50:05 +020030
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000031#include "405ep.h"
Dirk Eibach2da0fc02011-01-21 09:31:21 +010032#include <gdsys_fpga.h>
Dirk Eibacha605ea72010-10-21 10:50:05 +020033
Dirk Eibacha605ea72010-10-21 10:50:05 +020034#define REFLECTION_TESTPATTERN 0xdede
35#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
36
Dirk Eibach2da0fc02011-01-21 09:31:21 +010037DECLARE_GLOBAL_DATA_PTR;
38
39int get_fpga_state(unsigned dev)
40{
Simon Glass923a6622012-12-13 20:49:02 +000041 return gd->arch.fpga_state[dev];
Dirk Eibach2da0fc02011-01-21 09:31:21 +010042}
43
44void print_fpga_state(unsigned dev)
45{
Simon Glass923a6622012-12-13 20:49:02 +000046 if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
Dirk Eibach2da0fc02011-01-21 09:31:21 +010047 puts(" Waiting for FPGA-DONE timed out.\n");
Simon Glass923a6622012-12-13 20:49:02 +000048 if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
Dirk Eibach2da0fc02011-01-21 09:31:21 +010049 puts(" FPGA reflection test failed.\n");
50}
51
Dirk Eibacha605ea72010-10-21 10:50:05 +020052int board_early_init_f(void)
53{
Dirk Eibach2da0fc02011-01-21 09:31:21 +010054 unsigned k;
Dirk Eibach2da0fc02011-01-21 09:31:21 +010055
56 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
Simon Glass923a6622012-12-13 20:49:02 +000057 gd->arch.fpga_state[k] = 0;
Dirk Eibach2da0fc02011-01-21 09:31:21 +010058
Dirk Eibacha605ea72010-10-21 10:50:05 +020059 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
60 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
61 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
62 mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
63 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
64 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
65 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
66
67 /*
68 * EBC Configuration Register: set ready timeout to 512 ebc-clks
69 * -> ca. 15 us
70 */
71 mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000072 return 0;
73}
74
75int board_early_init_r(void)
76{
77 unsigned k;
78 unsigned ctr;
79
80 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
Simon Glass923a6622012-12-13 20:49:02 +000081 gd->arch.fpga_state[k] = 0;
Dirk Eibacha605ea72010-10-21 10:50:05 +020082
83 /*
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000084 * reset FPGA
Dirk Eibacha605ea72010-10-21 10:50:05 +020085 */
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000086 gd405ep_init();
Dirk Eibacha605ea72010-10-21 10:50:05 +020087
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000088 gd405ep_set_fpga_reset(1);
Dirk Eibacha605ea72010-10-21 10:50:05 +020089
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000090 gd405ep_setup_hw();
91
Dirk Eibach2da0fc02011-01-21 09:31:21 +010092 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
93 ctr = 0;
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000094 while (!gd405ep_get_fpga_done(k)) {
Dirk Eibach2da0fc02011-01-21 09:31:21 +010095 udelay(100000);
96 if (ctr++ > 5) {
Simon Glass923a6622012-12-13 20:49:02 +000097 gd->arch.fpga_state[k] |=
98 FPGA_STATE_DONE_FAILED;
Dirk Eibach2da0fc02011-01-21 09:31:21 +010099 break;
100 }
101 }
102 }
Dirk Eibacha605ea72010-10-21 10:50:05 +0200103
Dirk Eibacha605ea72010-10-21 10:50:05 +0200104 udelay(10);
Dirk Eibach6e9e6c32012-04-26 03:54:22 +0000105
106 gd405ep_set_fpga_reset(0);
Dirk Eibacha605ea72010-10-21 10:50:05 +0200107
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100108 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200109 struct ihs_fpga *fpga =
110 (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
Dirk Eibach5cb41002011-04-06 13:53:46 +0200111#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
112 u16 *reflection_target = &fpga->reflection_low;
113#else
114 u16 *reflection_target = &fpga->reflection_high;
115#endif
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100116 /*
117 * wait for fpga out of reset
118 */
119 ctr = 0;
120 while (1) {
121 out_le16(&fpga->reflection_low,
122 REFLECTION_TESTPATTERN);
Dirk Eibach5cb41002011-04-06 13:53:46 +0200123
124 if (in_le16(reflection_target) ==
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100125 REFLECTION_TESTPATTERN_INV)
126 break;
Dirk Eibach5cb41002011-04-06 13:53:46 +0200127
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100128 udelay(100000);
129 if (ctr++ > 5) {
Simon Glass923a6622012-12-13 20:49:02 +0000130 gd->arch.fpga_state[k] |=
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100131 FPGA_STATE_REFLECTION_FAILED;
132 break;
133 }
134 }
Dirk Eibacha605ea72010-10-21 10:50:05 +0200135 }
136
137 return 0;
138}