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Andy Fleming5f184712011-04-08 02:10:27 -05001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Andy Fleming <afleming@freescale.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 *
20 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
21 */
22
23#ifndef _PHY_H
24#define _PHY_H
25
26#include <linux/list.h>
27#include <linux/mii.h>
28#include <linux/ethtool.h>
29#include <linux/mdio.h>
30
31#define PHY_MAX_ADDR 32
32
33#define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
34 SUPPORTED_10baseT_Full | \
35 SUPPORTED_100baseT_Half | \
36 SUPPORTED_100baseT_Full | \
37 SUPPORTED_Autoneg | \
38 SUPPORTED_TP | \
39 SUPPORTED_MII)
40
41#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
42 SUPPORTED_1000baseT_Half | \
43 SUPPORTED_1000baseT_Full)
44
45#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
46 SUPPORTED_10000baseT_Full)
47
48#define PHY_ANEG_TIMEOUT 4000
49
50
51typedef enum {
52 PHY_INTERFACE_MODE_MII,
53 PHY_INTERFACE_MODE_GMII,
54 PHY_INTERFACE_MODE_SGMII,
Shaohui Xie7794b1a2013-03-25 07:39:31 +000055 PHY_INTERFACE_MODE_QSGMII,
Andy Fleming5f184712011-04-08 02:10:27 -050056 PHY_INTERFACE_MODE_TBI,
57 PHY_INTERFACE_MODE_RMII,
58 PHY_INTERFACE_MODE_RGMII,
59 PHY_INTERFACE_MODE_RGMII_ID,
60 PHY_INTERFACE_MODE_RGMII_RXID,
61 PHY_INTERFACE_MODE_RGMII_TXID,
62 PHY_INTERFACE_MODE_RTBI,
63 PHY_INTERFACE_MODE_XGMII,
64 PHY_INTERFACE_MODE_NONE /* Must be last */
65} phy_interface_t;
66
67static const char *phy_interface_strings[] = {
68 [PHY_INTERFACE_MODE_MII] = "mii",
69 [PHY_INTERFACE_MODE_GMII] = "gmii",
70 [PHY_INTERFACE_MODE_SGMII] = "sgmii",
Shaohui Xie7794b1a2013-03-25 07:39:31 +000071 [PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
Andy Fleming5f184712011-04-08 02:10:27 -050072 [PHY_INTERFACE_MODE_TBI] = "tbi",
73 [PHY_INTERFACE_MODE_RMII] = "rmii",
74 [PHY_INTERFACE_MODE_RGMII] = "rgmii",
75 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
76 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
77 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
78 [PHY_INTERFACE_MODE_RTBI] = "rtbi",
79 [PHY_INTERFACE_MODE_XGMII] = "xgmii",
80 [PHY_INTERFACE_MODE_NONE] = "",
81};
82
83static inline const char *phy_string_for_interface(phy_interface_t i)
84{
85 /* Default to unknown */
86 if (i > PHY_INTERFACE_MODE_NONE)
87 i = PHY_INTERFACE_MODE_NONE;
88
89 return phy_interface_strings[i];
90}
91
92
93struct phy_device;
94
95#define MDIO_NAME_LEN 32
96
97struct mii_dev {
98 struct list_head link;
99 char name[MDIO_NAME_LEN];
100 void *priv;
101 int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
102 int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
103 u16 val);
104 int (*reset)(struct mii_dev *bus);
105 struct phy_device *phymap[PHY_MAX_ADDR];
106 u32 phy_mask;
107};
108
109/* struct phy_driver: a structure which defines PHY behavior
110 *
111 * uid will contain a number which represents the PHY. During
112 * startup, the driver will poll the PHY to find out what its
113 * UID--as defined by registers 2 and 3--is. The 32-bit result
114 * gotten from the PHY will be masked to
115 * discard any bits which may change based on revision numbers
116 * unimportant to functionality
117 *
118 */
119struct phy_driver {
120 char *name;
121 unsigned int uid;
122 unsigned int mask;
123 unsigned int mmds;
124
125 u32 features;
126
127 /* Called to do any driver startup necessities */
128 /* Will be called during phy_connect */
129 int (*probe)(struct phy_device *phydev);
130
131 /* Called to configure the PHY, and modify the controller
132 * based on the results. Should be called after phy_connect */
133 int (*config)(struct phy_device *phydev);
134
135 /* Called when starting up the controller */
136 int (*startup)(struct phy_device *phydev);
137
138 /* Called when bringing down the controller */
139 int (*shutdown)(struct phy_device *phydev);
140
141 struct list_head list;
142};
143
144struct phy_device {
145 /* Information about the PHY type */
146 /* And management functions */
147 struct mii_dev *bus;
148 struct phy_driver *drv;
149 void *priv;
150
151 struct eth_device *dev;
152
153 /* forced speed & duplex (no autoneg)
154 * partner speed & duplex & pause (autoneg)
155 */
156 int speed;
157 int duplex;
158
159 /* The most recently read link state */
160 int link;
161 int port;
162 phy_interface_t interface;
163
164 u32 advertising;
165 u32 supported;
166 u32 mmds;
167
168 int autoneg;
169 int addr;
170 int pause;
171 int asym_pause;
172 u32 phy_id;
173 u32 flags;
174};
175
176static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
177{
178 struct mii_dev *bus = phydev->bus;
179
180 return bus->read(bus, phydev->addr, devad, regnum);
181}
182
183static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
184 u16 val)
185{
186 struct mii_dev *bus = phydev->bus;
187
188 return bus->write(bus, phydev->addr, devad, regnum, val);
189}
190
191#ifdef CONFIG_PHYLIB_10G
192extern struct phy_driver gen10g_driver;
193
194/* For now, XGMII is the only 10G interface */
195static inline int is_10g_interface(phy_interface_t interface)
196{
197 return interface == PHY_INTERFACE_MODE_XGMII;
198}
199
200#endif
201
202int phy_init(void);
203int phy_reset(struct phy_device *phydev);
Troy Kisky1adb4062012-10-22 16:40:43 +0000204struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
205 phy_interface_t interface);
206void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
Andy Fleming5f184712011-04-08 02:10:27 -0500207struct phy_device *phy_connect(struct mii_dev *bus, int addr,
208 struct eth_device *dev,
209 phy_interface_t interface);
210int phy_startup(struct phy_device *phydev);
211int phy_config(struct phy_device *phydev);
212int phy_shutdown(struct phy_device *phydev);
213int phy_register(struct phy_driver *drv);
214int genphy_config_aneg(struct phy_device *phydev);
Troy Kisky8682aba2012-02-07 14:08:48 +0000215int genphy_restart_aneg(struct phy_device *phydev);
Andy Fleming5f184712011-04-08 02:10:27 -0500216int genphy_update_link(struct phy_device *phydev);
217int genphy_config(struct phy_device *phydev);
218int genphy_startup(struct phy_device *phydev);
219int genphy_shutdown(struct phy_device *phydev);
220int gen10g_config(struct phy_device *phydev);
221int gen10g_startup(struct phy_device *phydev);
222int gen10g_shutdown(struct phy_device *phydev);
223int gen10g_discover_mmds(struct phy_device *phydev);
224
Andy Fleming9082eea2011-04-07 21:56:05 -0500225int phy_atheros_init(void);
226int phy_broadcom_init(void);
227int phy_davicom_init(void);
Matt Porterf485c8a2013-03-20 05:38:13 +0000228int phy_et1011c_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500229int phy_lxt_init(void);
230int phy_marvell_init(void);
231int phy_micrel_init(void);
232int phy_natsemi_init(void);
233int phy_realtek_init(void);
Vladimir Zapolskiyb6abf552011-12-29 15:18:37 +0000234int phy_smsc_init(void);
Andy Fleming9082eea2011-04-07 21:56:05 -0500235int phy_teranetics_init(void);
236int phy_vitesse_init(void);
Timur Tabia8366262011-10-18 18:44:34 -0500237
238/* PHY UIDs for various PHYs that are referenced in external code */
239#define PHY_UID_TN2020 0x00a19410
240
Andy Fleming5f184712011-04-08 02:10:27 -0500241#endif