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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roeseb0f80b92015-01-19 11:33:42 +01002
3#include <config.h>
Stefan Roeseb0f80b92015-01-19 11:33:42 +01004#include <linux/linkage.h>
5
Pali Rohár701769d2021-10-21 16:46:08 +02006/*
7 * BootROM loads the header part of kwbimage into L2 cache. BIN header usually
8 * contains U-Boot SPL, optionally it can also contain additional arguments.
9 * The number of these arguments is in r0, pointer to the argument array in r1.
10 * BootROM expects executable BIN header code to return to address stored in lr.
11 * Other registers (r2 - r12) must be preserved. We save all registers to
12 * CONFIG_SPL_BOOTROM_SAVE address. BIN header arguments (passed via r0 and r1)
13 * are currently not used by U-Boot SPL binary.
14 */
Stefan Roese944c7a32015-08-25 13:49:41 +020015ENTRY(save_boot_params)
16 stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
17 ldr r12, =CONFIG_SPL_BOOTROM_SAVE
18 str sp, [r12]
19 b save_boot_params_ret
20ENDPROC(save_boot_params)
21
22ENTRY(return_to_bootrom)
23 ldr r12, =CONFIG_SPL_BOOTROM_SAVE
24 ldr sp, [r12]
Pali Rohár43755982021-07-23 11:14:23 +020025 ldmfd sp!, {r0 - r12, lr} /* @ restore registers from stack */
Stefan Roese944c7a32015-08-25 13:49:41 +020026 mov r0, #0x0 /* @ return value: 0x0 NO_ERR */
Pali Rohár43755982021-07-23 11:14:23 +020027 bx lr /* @ return to bootrom */
Stefan Roese944c7a32015-08-25 13:49:41 +020028ENDPROC(return_to_bootrom)
Stefan Roeseb0f80b92015-01-19 11:33:42 +010029
30/*
31 * cache_inv - invalidate Cache line
32 * r0 - dest
33 */
34 .global cache_inv
35 .type cache_inv, %function
36 cache_inv:
37
38 stmfd sp!, {r1-r12}
39
40 mcr p15, 0, r0, c7, c6, 1
41
42 ldmfd sp!, {r1-r12}
43 bx lr
44
45
46/*
47 * flush_l1_v6 - l1 cache clean invalidate
48 * r0 - dest
49 */
50 .global flush_l1_v6
51 .type flush_l1_v6, %function
52 flush_l1_v6:
53
54 stmfd sp!, {r1-r12}
55
56 mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
57 mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
58 mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
59
60 ldmfd sp!, {r1-r12}
61 bx lr
62
63
64/*
65 * flush_l1_v7 - l1 cache clean invalidate
66 * r0 - dest
67 */
68 .global flush_l1_v7
69 .type flush_l1_v7, %function
70 flush_l1_v7:
71
72 stmfd sp!, {r1-r12}
73
74 dmb /* @data memory barrier */
75 mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
76 dsb /* @data sync barrier */
77
78 ldmfd sp!, {r1-r12}
79 bx lr