Dan Murphy | 2d2358a | 2013-08-26 08:54:52 -0500 | [diff] [blame] | 1 | /* |
| 2 | * OMAP USB HOST xHCI Controller |
| 3 | * |
| 4 | * (C) Copyright 2013 |
| 5 | * Texas Instruments, <www.ti.com> |
| 6 | * |
| 7 | * Author: Dan Murphy <dmurphy@ti.com> |
| 8 | * |
| 9 | * SPDX-License-Identifier: GPL-2.0+ |
| 10 | */ |
| 11 | |
| 12 | #include <common.h> |
| 13 | #include <usb.h> |
| 14 | #include <asm-generic/errno.h> |
| 15 | #include <asm/omap_common.h> |
| 16 | #include <asm/arch/cpu.h> |
| 17 | #include <asm/arch/sys_proto.h> |
Dan Murphy | 2d2358a | 2013-08-26 08:54:52 -0500 | [diff] [blame] | 18 | |
| 19 | #include <linux/compat.h> |
| 20 | #include <linux/usb/dwc3.h> |
Dan Murphy | 41b667b | 2013-10-11 12:28:14 -0500 | [diff] [blame] | 21 | #include <linux/usb/xhci-omap.h> |
Dan Murphy | 2d2358a | 2013-08-26 08:54:52 -0500 | [diff] [blame] | 22 | |
| 23 | #include "xhci.h" |
| 24 | |
| 25 | /* Declare global data pointer */ |
| 26 | DECLARE_GLOBAL_DATA_PTR; |
| 27 | |
| 28 | static struct omap_xhci omap; |
| 29 | |
Troy Kisky | 7e575c4 | 2013-10-22 14:27:17 -0700 | [diff] [blame] | 30 | inline int __board_usb_init(int index, enum usb_init_type init) |
Dan Murphy | 2d2358a | 2013-08-26 08:54:52 -0500 | [diff] [blame] | 31 | { |
| 32 | return 0; |
| 33 | } |
Troy Kisky | 7e575c4 | 2013-10-22 14:27:17 -0700 | [diff] [blame] | 34 | int board_usb_init(int index, enum usb_init_type init) |
Dan Murphy | b216821 | 2013-10-11 12:28:15 -0500 | [diff] [blame] | 35 | __attribute__((weak, alias("__board_usb_init"))); |
Dan Murphy | 2d2358a | 2013-08-26 08:54:52 -0500 | [diff] [blame] | 36 | |
| 37 | static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) |
| 38 | { |
| 39 | clrsetbits_le32(&dwc3_reg->g_ctl, |
| 40 | DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), |
| 41 | DWC3_GCTL_PRTCAPDIR(mode)); |
| 42 | } |
| 43 | |
| 44 | static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) |
| 45 | { |
| 46 | /* Before Resetting PHY, put Core in Reset */ |
| 47 | setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); |
| 48 | |
Dan Murphy | ba55453 | 2013-10-11 12:28:16 -0500 | [diff] [blame] | 49 | omap_reset_usb_phy(dwc3_reg); |
Dan Murphy | 2d2358a | 2013-08-26 08:54:52 -0500 | [diff] [blame] | 50 | |
| 51 | /* After PHYs are stable we can take Core out of reset state */ |
| 52 | clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); |
| 53 | } |
| 54 | |
| 55 | static int dwc3_core_init(struct dwc3 *dwc3_reg) |
| 56 | { |
| 57 | u32 reg; |
| 58 | u32 revision; |
| 59 | unsigned int dwc3_hwparams1; |
| 60 | |
| 61 | revision = readl(&dwc3_reg->g_snpsid); |
| 62 | /* This should read as U3 followed by revision number */ |
| 63 | if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { |
| 64 | puts("this is not a DesignWare USB3 DRD Core\n"); |
| 65 | return -1; |
| 66 | } |
| 67 | |
| 68 | dwc3_core_soft_reset(dwc3_reg); |
| 69 | |
| 70 | dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); |
| 71 | |
| 72 | reg = readl(&dwc3_reg->g_ctl); |
| 73 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
| 74 | reg &= ~DWC3_GCTL_DISSCRAMBLE; |
| 75 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { |
| 76 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
| 77 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; |
| 78 | break; |
| 79 | default: |
| 80 | debug("No power optimization available\n"); |
| 81 | } |
| 82 | |
| 83 | /* |
| 84 | * WORKAROUND: DWC3 revisions <1.90a have a bug |
| 85 | * where the device can fail to connect at SuperSpeed |
| 86 | * and falls back to high-speed mode which causes |
| 87 | * the device to enter a Connect/Disconnect loop |
| 88 | */ |
| 89 | if ((revision & DWC3_REVISION_MASK) < 0x190a) |
| 90 | reg |= DWC3_GCTL_U2RSTECN; |
| 91 | |
| 92 | writel(reg, &dwc3_reg->g_ctl); |
| 93 | |
| 94 | return 0; |
| 95 | } |
| 96 | |
| 97 | static int omap_xhci_core_init(struct omap_xhci *omap) |
| 98 | { |
| 99 | int ret = 0; |
| 100 | |
Dan Murphy | 834e91a | 2013-10-11 12:28:17 -0500 | [diff] [blame] | 101 | omap_enable_phy(omap); |
Dan Murphy | 2d2358a | 2013-08-26 08:54:52 -0500 | [diff] [blame] | 102 | |
| 103 | ret = dwc3_core_init(omap->dwc3_reg); |
| 104 | if (ret) { |
| 105 | debug("%s:failed to initialize core\n", __func__); |
| 106 | return ret; |
| 107 | } |
| 108 | |
| 109 | /* We are hard-coding DWC3 core to Host Mode */ |
| 110 | dwc3_set_mode(omap->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); |
| 111 | |
| 112 | return ret; |
| 113 | } |
| 114 | |
| 115 | static void omap_xhci_core_exit(struct omap_xhci *omap) |
| 116 | { |
Dan Murphy | 834e91a | 2013-10-11 12:28:17 -0500 | [diff] [blame] | 117 | usb_phy_power(0); |
Dan Murphy | 2d2358a | 2013-08-26 08:54:52 -0500 | [diff] [blame] | 118 | } |
| 119 | |
| 120 | int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) |
| 121 | { |
| 122 | struct omap_xhci *ctx = &omap; |
| 123 | int ret = 0; |
| 124 | |
| 125 | ctx->hcd = (struct xhci_hccr *)OMAP_XHCI_BASE; |
| 126 | ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); |
| 127 | ctx->usb3_phy = (struct omap_usb3_phy *)OMAP_OCP1_SCP_BASE; |
| 128 | ctx->otg_wrapper = (struct omap_dwc_wrapper *)OMAP_OTG_WRAPPER_BASE; |
| 129 | |
Dan Murphy | b216821 | 2013-10-11 12:28:15 -0500 | [diff] [blame] | 130 | ret = board_usb_init(index, USB_INIT_HOST); |
Dan Murphy | 2d2358a | 2013-08-26 08:54:52 -0500 | [diff] [blame] | 131 | if (ret != 0) { |
| 132 | puts("Failed to initialize board for USB\n"); |
| 133 | return ret; |
| 134 | } |
| 135 | |
| 136 | ret = omap_xhci_core_init(ctx); |
| 137 | if (ret < 0) { |
| 138 | puts("Failed to initialize xhci\n"); |
| 139 | return ret; |
| 140 | } |
| 141 | |
| 142 | *hccr = (struct xhci_hccr *)(OMAP_XHCI_BASE); |
| 143 | *hcor = (struct xhci_hcor *)((uint32_t) *hccr |
| 144 | + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); |
| 145 | |
| 146 | debug("omap-xhci: init hccr %x and hcor %x hc_length %d\n", |
| 147 | (uint32_t)*hccr, (uint32_t)*hcor, |
| 148 | (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); |
| 149 | |
| 150 | return ret; |
| 151 | } |
| 152 | |
| 153 | void xhci_hcd_stop(int index) |
| 154 | { |
| 155 | struct omap_xhci *ctx = &omap; |
| 156 | |
| 157 | omap_xhci_core_exit(ctx); |
| 158 | } |