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Kumar Galaec2b74f2008-01-17 16:48:33 -06001/*
Kumar Gala4194b362010-01-12 11:42:43 -06002 * Copyright 2008-2010 Freescale Semiconductor, Inc.
Kumar Galaec2b74f2008-01-17 16:48:33 -06003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <asm/processor.h>
25#include <ioports.h>
Kumar Galadd6c9102008-03-26 08:53:53 -050026#include <lmb.h>
Kumar Galaec2b74f2008-01-17 16:48:33 -060027#include <asm/io.h>
Kumar Galac7259082009-09-03 08:41:31 -050028#include <asm/mmu.h>
Kumar Gala39a7e7f2009-09-17 01:44:39 -050029#include <asm/fsl_law.h>
Kumar Galaec2b74f2008-01-17 16:48:33 -060030#include "mp.h"
31
32DECLARE_GLOBAL_DATA_PTR;
33
Kumar Galaec2b74f2008-01-17 16:48:33 -060034u32 get_my_id()
35{
36 return mfspr(SPRN_PIR);
37}
38
39int cpu_reset(int nr)
40{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
Kumar Galaec2b74f2008-01-17 16:48:33 -060042 out_be32(&pic->pir, 1 << nr);
Kumar Galac840d262009-03-31 23:11:05 -050043 /* the dummy read works around an errata on early 85xx MP PICs */
Kumar Galaec2b74f2008-01-17 16:48:33 -060044 (void)in_be32(&pic->pir);
45 out_be32(&pic->pir, 0x0);
46
47 return 0;
48}
49
50int cpu_status(int nr)
51{
52 u32 *table, id = get_my_id();
53
54 if (nr == id) {
Peter Tyser5ccd29c2009-10-23 15:55:47 -050055 table = (u32 *)get_spin_virt_addr();
Kumar Gala348753d2008-07-14 14:03:02 -050056 printf("table base @ 0x%p\n", table);
Kumar Galaec2b74f2008-01-17 16:48:33 -060057 } else {
Peter Tyser5ccd29c2009-10-23 15:55:47 -050058 table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
Kumar Galaec2b74f2008-01-17 16:48:33 -060059 printf("Running on cpu %d\n", id);
60 printf("\n");
Kumar Gala348753d2008-07-14 14:03:02 -050061 printf("table @ 0x%p\n", table);
Kumar Gala79679d82008-03-26 08:34:25 -050062 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
Kumar Galaec2b74f2008-01-17 16:48:33 -060063 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
Kumar Gala79679d82008-03-26 08:34:25 -050064 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
65 printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
Kumar Galaec2b74f2008-01-17 16:48:33 -060066 }
67
68 return 0;
69}
70
Kumar Galaa9c3ac72010-01-12 12:56:05 -060071#ifdef CONFIG_FSL_CORENET
Kumar Gala4194b362010-01-12 11:42:43 -060072int cpu_disable(int nr)
73{
Kumar Galaa9c3ac72010-01-12 12:56:05 -060074 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
75
76 setbits_be32(&gur->coredisrl, 1 << nr);
77
78 return 0;
Kumar Gala4194b362010-01-12 11:42:43 -060079}
Kumar Galaa9c3ac72010-01-12 12:56:05 -060080#else
81int cpu_disable(int nr)
82{
83 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
84
85 switch (nr) {
86 case 0:
87 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
88 break;
89 case 1:
90 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
91 break;
92 default:
93 printf("Invalid cpu number for disable %d\n", nr);
94 return 1;
95 }
96
97 return 0;
98}
99#endif
Kumar Gala4194b362010-01-12 11:42:43 -0600100
Kumar Gala79679d82008-03-26 08:34:25 -0500101static u8 boot_entry_map[4] = {
102 0,
103 BOOT_ENTRY_PIR,
104 BOOT_ENTRY_R3_LOWER,
105 BOOT_ENTRY_R6_LOWER,
106};
107
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200108int cpu_release(int nr, int argc, char * const argv[])
Kumar Galaec2b74f2008-01-17 16:48:33 -0600109{
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500110 u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
Kumar Gala79679d82008-03-26 08:34:25 -0500111 u64 boot_addr;
Kumar Galaec2b74f2008-01-17 16:48:33 -0600112
113 if (nr == get_my_id()) {
114 printf("Invalid to release the boot core.\n\n");
115 return 1;
116 }
117
Kumar Gala79679d82008-03-26 08:34:25 -0500118 if (argc != 4) {
Kumar Galaec2b74f2008-01-17 16:48:33 -0600119 printf("Invalid number of arguments to release.\n\n");
120 return 1;
121 }
122
Kumar Gala79679d82008-03-26 08:34:25 -0500123 boot_addr = simple_strtoull(argv[0], NULL, 16);
Kumar Gala79679d82008-03-26 08:34:25 -0500124
125 /* handle pir, r3, r6 */
126 for (i = 1; i < 4; i++) {
Kumar Galaec2b74f2008-01-17 16:48:33 -0600127 if (argv[i][0] != '-') {
Kumar Gala79679d82008-03-26 08:34:25 -0500128 u8 entry = boot_entry_map[i];
Kumar Galaec2b74f2008-01-17 16:48:33 -0600129 val = simple_strtoul(argv[i], NULL, 16);
Kumar Gala79679d82008-03-26 08:34:25 -0500130 table[entry] = val;
Kumar Galaec2b74f2008-01-17 16:48:33 -0600131 }
132 }
133
Kumar Gala79679d82008-03-26 08:34:25 -0500134 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
Kumar Galacf6cc012008-04-28 02:24:04 -0500135
136 /* ensure all table updates complete before final address write */
137 eieio();
138
Kumar Gala79679d82008-03-26 08:34:25 -0500139 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
Kumar Galaec2b74f2008-01-17 16:48:33 -0600140
141 return 0;
142}
143
Kumar Galac840d262009-03-31 23:11:05 -0500144u32 determine_mp_bootpg(void)
145{
146 /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
147 if ((u64)gd->ram_size > 0xfffff000)
148 return (0xfffff000);
149
150 return (gd->ram_size - 4096);
151}
152
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500153ulong get_spin_phys_addr(void)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600154{
155 extern ulong __secondary_start_page;
156 extern ulong __spin_table;
157
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500158 return (determine_mp_bootpg() +
159 (ulong)&__spin_table - (ulong)&__secondary_start_page);
160}
Kumar Galaec2b74f2008-01-17 16:48:33 -0600161
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500162ulong get_spin_virt_addr(void)
163{
164 extern ulong __secondary_start_page;
165 extern ulong __spin_table;
166
167 return (CONFIG_BPTR_VIRT_ADDR +
168 (ulong)&__spin_table - (ulong)&__secondary_start_page);
Kumar Galaec2b74f2008-01-17 16:48:33 -0600169}
170
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500171#ifdef CONFIG_FSL_CORENET
172static void plat_mp_up(unsigned long bootpg)
173{
174 u32 up, cpu_up_mask, whoami;
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500175 u32 *table = (u32 *)get_spin_virt_addr();
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500176 volatile ccsr_gur_t *gur;
177 volatile ccsr_local_t *ccm;
178 volatile ccsr_rcpm_t *rcpm;
179 volatile ccsr_pic_t *pic;
180 int timeout = 10;
181 u32 nr_cpus;
182 struct law_entry e;
183
184 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
185 ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
186 rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
187 pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
188
189 nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
190
191 whoami = in_be32(&pic->whoami);
192 cpu_up_mask = 1 << whoami;
193 out_be32(&ccm->bstrl, bootpg);
194
195 e = find_law(bootpg);
196 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K);
197
Dave Liuf5ecc6e2009-11-17 20:01:24 -0600198 /* readback to sync write */
199 in_be32(&ccm->bstrar);
200
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500201 /* disable time base at the platform */
202 out_be32(&rcpm->ctbenrl, cpu_up_mask);
203
204 /* release the hounds */
205 up = ((1 << nr_cpus) - 1);
206 out_be32(&gur->brrl, up);
207
208 /* wait for everyone */
209 while (timeout) {
210 int i;
211 for (i = 0; i < nr_cpus; i++) {
212 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
213 cpu_up_mask |= (1 << i);
214 };
215
216 if ((cpu_up_mask & up) == up)
217 break;
218
219 udelay(100);
220 timeout--;
221 }
222
223 if (timeout == 0)
224 printf("CPU up timeout. CPU up mask is %x should be %x\n",
225 cpu_up_mask, up);
226
227 /* enable time base at the platform */
228 out_be32(&rcpm->ctbenrl, 0);
229 mtspr(SPRN_TBWU, 0);
230 mtspr(SPRN_TBWL, 0);
231 out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500232
233#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
234 /*
235 * Disabling Boot Page Translation allows the memory region 0xfffff000
236 * to 0xffffffff to be used normally. Leaving Boot Page Translation
237 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
238 * unusable for normal operation but it does allow OSes to easily
239 * reset a processor core to put it back into U-Boot's spinloop.
240 */
241 clrbits_be32(&ecm->bptr, 0x80000000);
242#endif
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500243}
244#else
245static void plat_mp_up(unsigned long bootpg)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600246{
247 u32 up, cpu_up_mask, whoami;
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500248 u32 *table = (u32 *)get_spin_virt_addr();
Kumar Galaec2b74f2008-01-17 16:48:33 -0600249 volatile u32 bpcr;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
251 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
252 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
Kumar Galaec2b74f2008-01-17 16:48:33 -0600253 u32 devdisr;
254 int timeout = 10;
255
256 whoami = in_be32(&pic->whoami);
257 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
258
259 /* disable time base at the platform */
260 devdisr = in_be32(&gur->devdisr);
261 if (whoami)
262 devdisr |= MPC85xx_DEVDISR_TB0;
263 else
264 devdisr |= MPC85xx_DEVDISR_TB1;
265 out_be32(&gur->devdisr, devdisr);
266
267 /* release the hounds */
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530268 up = ((1 << cpu_numcores()) - 1);
Kumar Galaec2b74f2008-01-17 16:48:33 -0600269 bpcr = in_be32(&ecm->eebpcr);
270 bpcr |= (up << 24);
271 out_be32(&ecm->eebpcr, bpcr);
272 asm("sync; isync; msync");
273
274 cpu_up_mask = 1 << whoami;
275 /* wait for everyone */
276 while (timeout) {
277 int i;
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530278 for (i = 0; i < cpu_numcores(); i++) {
Kumar Gala97b3ecb2008-04-09 04:20:57 -0500279 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
Kumar Galaec2b74f2008-01-17 16:48:33 -0600280 cpu_up_mask |= (1 << i);
281 };
282
283 if ((cpu_up_mask & up) == up)
284 break;
285
286 udelay(100);
287 timeout--;
288 }
289
Kumar Gala97b3ecb2008-04-09 04:20:57 -0500290 if (timeout == 0)
291 printf("CPU up timeout. CPU up mask is %x should be %x\n",
292 cpu_up_mask, up);
293
Kumar Galaec2b74f2008-01-17 16:48:33 -0600294 /* enable time base at the platform */
295 if (whoami)
296 devdisr |= MPC85xx_DEVDISR_TB1;
297 else
298 devdisr |= MPC85xx_DEVDISR_TB0;
299 out_be32(&gur->devdisr, devdisr);
300 mtspr(SPRN_TBWU, 0);
301 mtspr(SPRN_TBWL, 0);
302
303 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
304 out_be32(&gur->devdisr, devdisr);
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500305
306#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
307 /*
308 * Disabling Boot Page Translation allows the memory region 0xfffff000
309 * to 0xffffffff to be used normally. Leaving Boot Page Translation
310 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
311 * unusable for normal operation but it does allow OSes to easily
312 * reset a processor core to put it back into U-Boot's spinloop.
313 */
314 clrbits_be32(&ecm->bptr, 0x80000000);
315#endif
Kumar Galaec2b74f2008-01-17 16:48:33 -0600316}
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500317#endif
Kumar Galaec2b74f2008-01-17 16:48:33 -0600318
Kumar Galadd6c9102008-03-26 08:53:53 -0500319void cpu_mp_lmb_reserve(struct lmb *lmb)
320{
Kumar Galac840d262009-03-31 23:11:05 -0500321 u32 bootpg = determine_mp_bootpg();
Kumar Galadd6c9102008-03-26 08:53:53 -0500322
323 lmb_reserve(lmb, bootpg, 4096);
324}
325
Kumar Galaec2b74f2008-01-17 16:48:33 -0600326void setup_mp(void)
327{
328 extern ulong __secondary_start_page;
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500329 extern ulong __bootpg_addr;
Kumar Galaec2b74f2008-01-17 16:48:33 -0600330 ulong fixup = (ulong)&__secondary_start_page;
Kumar Galac840d262009-03-31 23:11:05 -0500331 u32 bootpg = determine_mp_bootpg();
Kumar Galaec2b74f2008-01-17 16:48:33 -0600332
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500333 /* Store the bootpg's SDRAM address for use by secondary CPU cores */
334 __bootpg_addr = bootpg;
335
Kumar Galac7259082009-09-03 08:41:31 -0500336 /* look for the tlb covering the reset page, there better be one */
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500337 int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
Kumar Galaec2b74f2008-01-17 16:48:33 -0600338
Kumar Galac7259082009-09-03 08:41:31 -0500339 /* we found a match */
340 if (i != -1) {
341 /* map reset page to bootpg so we can copy code there */
342 disable_tlb(i);
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500343
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500344 set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
Kumar Galaabc76eb2009-11-17 20:21:20 -0600345 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
Kumar Galac7259082009-09-03 08:41:31 -0500346 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
347
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500348 memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
349
Kumar Gala39a7e7f2009-09-17 01:44:39 -0500350 plat_mp_up(bootpg);
Kumar Galac7259082009-09-03 08:41:31 -0500351 } else {
352 puts("WARNING: No reset page TLB. "
353 "Skipping secondary core setup\n");
354 }
Kumar Galaec2b74f2008-01-17 16:48:33 -0600355}