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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00006 */
7
8#include <common.h>
9#include <mpc8260.h>
10#include <asm/processor.h>
11
Heiko Schocherfa230442006-12-21 17:17:02 +010012#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
13extern unsigned long board_get_cpu_clk_f (void);
14#endif
15
Wolfgang Denkd87080b2006-03-31 18:32:53 +020016DECLARE_GLOBAL_DATA_PTR;
17
wdenk4a9cbbe2002-08-27 09:48:53 +000018/* ------------------------------------------------------------------------- */
19
20/* Bus-to-Core Multiplier */
21#define _1x 2
22#define _1_5x 3
23#define _2x 4
24#define _2_5x 5
25#define _3x 6
26#define _3_5x 7
27#define _4x 8
28#define _4_5x 9
29#define _5x 10
30#define _5_5x 11
31#define _6x 12
32#define _6_5x 13
33#define _7x 14
34#define _7_5x 15
35#define _8x 16
36#define _byp -1
37#define _off -2
38#define _unk -3
39
40typedef struct {
41 int b2c_mult;
42 int vco_div;
43 char *freq_60x;
44 char *freq_core;
45} corecnf_t;
46
47/*
48 * this table based on "Errata to MPC8260 PowerQUICC II User's Manual",
49 * Rev. 1, 8/2000, page 10.
50 */
51corecnf_t corecnf_tab[] = {
52 { _1_5x, 4, " 33-100", " 33-100" }, /* 0x00 */
53 { _1x, 4, " 50-150", " 50-150" }, /* 0x01 */
54 { _1x, 8, " 25-75 ", " 25-75 " }, /* 0x02 */
55 { _byp, -1, " ?-? ", " ?-? " }, /* 0x03 */
56 { _2x, 2, " 50-150", "100-300" }, /* 0x04 */
57 { _2x, 4, " 25-75 ", " 50-150" }, /* 0x05 */
58 { _2_5x, 2, " 40-120", "100-240" }, /* 0x06 */
59 { _4_5x, 2, " 22-65 ", "100-300" }, /* 0x07 */
60 { _3x, 2, " 33-100", "100-300" }, /* 0x08 */
61 { _5_5x, 2, " 18-55 ", "100-300" }, /* 0x09 */
62 { _4x, 2, " 25-75 ", "100-300" }, /* 0x0A */
63 { _5x, 2, " 20-60 ", "100-300" }, /* 0x0B */
64 { _1_5x, 8, " 16-50 ", " 16-50 " }, /* 0x0C */
65 { _6x, 2, " 16-50 ", "100-300" }, /* 0x0D */
66 { _3_5x, 2, " 30-85 ", "100-300" }, /* 0x0E */
67 { _off, -1, " ?-? ", " ?-? " }, /* 0x0F */
68 { _3x, 4, " 16-50 ", " 50-150" }, /* 0x10 */
69 { _2_5x, 4, " 20-60 ", " 50-120" }, /* 0x11 */
70 { _6_5x, 2, " 15-46 ", "100-300" }, /* 0x12 */
71 { _byp, -1, " ?-? ", " ?-? " }, /* 0x13 */
72 { _7x, 2, " 14-43 ", "100-300" }, /* 0x14 */
73 { _2x, 4, " 25-75 ", " 50-150" }, /* 0x15 */
74 { _7_5x, 2, " 13-40 ", "100-300" }, /* 0x16 */
75 { _4_5x, 2, " 22-65 ", "100-300" }, /* 0x17 */
76 { _unk, -1, " ?-? ", " ?-? " }, /* 0x18 */
77 { _5_5x, 2, " 18-55 ", "100-300" }, /* 0x19 */
78 { _4x, 2, " 25-75 ", "100-300" }, /* 0x1A */
79 { _5x, 2, " 20-60 ", "100-300" }, /* 0x1B */
80 { _8x, 2, " 12-38 ", "100-300" }, /* 0x1C */
81 { _6x, 2, " 16-50 ", "100-300" }, /* 0x1D */
82 { _3_5x, 2, " 30-85 ", "100-300" }, /* 0x1E */
83 { _off, -1, " ?-? ", " ?-? " }, /* 0x1F */
84};
85
86/* ------------------------------------------------------------------------- */
87
88/*
89 *
90 */
91
92int get_clocks (void)
93{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk4a9cbbe2002-08-27 09:48:53 +000095 ulong clkin;
96 ulong sccr, dfbrg;
Wolfgang Denk89a7b782011-11-04 15:55:52 +000097 ulong scmr, corecnf, plldf, pllmf;
wdenk4a9cbbe2002-08-27 09:48:53 +000098 corecnf_t *cp;
99
100#if !defined(CONFIG_8260_CLKIN)
101#error clock measuring not implemented yet - define CONFIG_8260_CLKIN
102#else
Heiko Schocherfa230442006-12-21 17:17:02 +0100103#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
104 clkin = board_get_cpu_clk_f ();
105#else
wdenk4a9cbbe2002-08-27 09:48:53 +0000106 clkin = CONFIG_8260_CLKIN;
107#endif
Heiko Schocherfa230442006-12-21 17:17:02 +0100108#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000109
110 sccr = immap->im_clkrst.car_sccr;
111 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
112
113 scmr = immap->im_clkrst.car_scmr;
114 corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
wdenk4a9cbbe2002-08-27 09:48:53 +0000115 cp = &corecnf_tab[corecnf];
116
wdenke1599e82004-10-10 23:27:33 +0000117 /* HiP7, HiP7 Rev01, HiP7 RevA */
118 if ((get_pvr () == PVR_8260_HIP7) ||
119 (get_pvr () == PVR_8260_HIP7R1) ||
120 (get_pvr () == PVR_8260_HIP7RA)) {
wdenk8564acf2003-07-14 22:13:32 +0000121 pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT;
Simon Glass748cd052012-12-13 20:48:46 +0000122 gd->arch.vco_out = clkin * (pllmf + 1);
wdenk8564acf2003-07-14 22:13:32 +0000123 } else { /* HiP3, HiP4 */
124 pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
125 plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
Simon Glass748cd052012-12-13 20:48:46 +0000126 gd->arch.vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
wdenk8564acf2003-07-14 22:13:32 +0000127 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000128
Simon Glass748cd052012-12-13 20:48:46 +0000129 gd->arch.cpm_clk = gd->arch.vco_out / 2;
wdenk4a9cbbe2002-08-27 09:48:53 +0000130 gd->bus_clk = clkin;
Simon Glass748cd052012-12-13 20:48:46 +0000131 gd->arch.scc_clk = gd->arch.vco_out / 4;
132 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
wdenk4a9cbbe2002-08-27 09:48:53 +0000133
134 if (cp->b2c_mult > 0) {
135 gd->cpu_clk = (clkin * cp->b2c_mult) / 2;
136 } else {
137 gd->cpu_clk = clkin;
138 }
139
Stefan Roesef2302d42008-08-06 14:05:38 +0200140#ifdef CONFIG_PCI
141 gd->pci_clk = clkin;
142
143 if (sccr & SCCR_PCI_MODE) {
144 uint pci_div;
145 uint pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT;
146
147 if (sccr & SCCR_PCI_MODCK) {
148 pci_div = 2;
149 if (pcidf == 9) {
150 pci_div *= 5;
151 } else if (pcidf == 0xB) {
152 pci_div *= 6;
153 } else {
154 pci_div *= (pcidf + 1);
155 }
156 } else {
157 pci_div = pcidf + 1;
158 }
159
Simon Glass748cd052012-12-13 20:48:46 +0000160 gd->pci_clk = (gd->arch.cpm_clk * 2) / pci_div;
Stefan Roesef2302d42008-08-06 14:05:38 +0200161 }
162#endif
163
wdenk4a9cbbe2002-08-27 09:48:53 +0000164 return (0);
165}
166
167int prt_8260_clks (void)
168{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk4a9cbbe2002-08-27 09:48:53 +0000170 ulong sccr, dfbrg;
Wolfgang Denk23466d62006-03-12 16:14:29 +0100171 ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf, pcidf;
wdenk4a9cbbe2002-08-27 09:48:53 +0000172 corecnf_t *cp;
173
174 sccr = immap->im_clkrst.car_sccr;
175 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
176
177 scmr = immap->im_clkrst.car_scmr;
178 corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
179 busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
180 cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
181 plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
182 pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
Wolfgang Denk23466d62006-03-12 16:14:29 +0100183 pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT;
wdenk4a9cbbe2002-08-27 09:48:53 +0000184
185 cp = &corecnf_tab[corecnf];
186
wdenk4b9206e2004-03-23 22:14:11 +0000187 puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");
wdenk4a9cbbe2002-08-27 09:48:53 +0000188
189 switch (cp->b2c_mult) {
190 case _byp:
wdenk4b9206e2004-03-23 22:14:11 +0000191 puts ("BYPASS");
wdenk4a9cbbe2002-08-27 09:48:53 +0000192 break;
193
194 case _off:
wdenk4b9206e2004-03-23 22:14:11 +0000195 puts ("OFF");
wdenk4a9cbbe2002-08-27 09:48:53 +0000196 break;
197
198 case _unk:
wdenk4b9206e2004-03-23 22:14:11 +0000199 puts ("UNKNOWN");
wdenk4a9cbbe2002-08-27 09:48:53 +0000200 break;
201
202 default:
203 printf ("%d%sx",
204 cp->b2c_mult / 2,
205 (cp->b2c_mult % 2) ? ".5" : "");
206 break;
207 }
208
209 printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
210 cp->vco_div, cp->freq_60x, cp->freq_core);
211
212 printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
Wolfgang Denk23466d62006-03-12 16:14:29 +0100213 "plldf %ld, pllmf %ld, pcidf %ld\n",
214 dfbrg, corecnf, busdf, cpmdf,
215 plldf, pllmf, pcidf);
wdenk4a9cbbe2002-08-27 09:48:53 +0000216
217 printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
Simon Glass748cd052012-12-13 20:48:46 +0000218 gd->arch.vco_out, gd->arch.scc_clk, gd->arch.brg_clk);
wdenk4a9cbbe2002-08-27 09:48:53 +0000219
wdenk4b9206e2004-03-23 22:14:11 +0000220 printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
Simon Glass748cd052012-12-13 20:48:46 +0000221 gd->cpu_clk, gd->arch.cpm_clk, gd->bus_clk);
Stefan Roesef2302d42008-08-06 14:05:38 +0200222#ifdef CONFIG_PCI
223 printf (" - pci_clk %10ld\n", gd->pci_clk);
224#endif
wdenk4b9206e2004-03-23 22:14:11 +0000225 putc ('\n');
226
wdenk4a9cbbe2002-08-27 09:48:53 +0000227 return (0);
228}