| wdenk | 8ed9604 | 2005-01-09 23:16:25 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2004 |
| 3 | * Texas Instruments, <www.ti.com> |
| 4 | * Richard Woodruff <r-woodruff2@ti.com> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #ifndef _OMAP2420_SYS_H_ |
| 26 | #define _OMAP2420_SYS_H_ |
| 27 | |
| 28 | #include <asm/arch/sizes.h> |
| 29 | |
| 30 | /* |
| 31 | * 2420 specific Section |
| 32 | */ |
| 33 | |
| 34 | /* CONTROL */ |
| 35 | #define OMAP2420_CTRL_BASE (0x48000000) |
| 36 | #define CONTROL_STATUS (OMAP2420_CTRL_BASE + 0x2F8) |
| 37 | |
| 38 | /* TAP information */ |
| 39 | #define OMAP2420_TAP_BASE (0x48014000) |
| 40 | #define TAP_IDCODE_REG (OMAP2420_TAP_BASE+0x204) |
| 41 | |
| 42 | /* GPMC */ |
| 43 | #define OMAP2420_GPMC_BASE (0x6800A000) |
| 44 | #define GPMC_SYSCONFIG (OMAP2420_GPMC_BASE+0x10) |
| 45 | #define GPMC_IRQENABLE (OMAP2420_GPMC_BASE+0x1C) |
| 46 | #define GPMC_TIMEOUT_CONTROL (OMAP2420_GPMC_BASE+0x40) |
| 47 | #define GPMC_CONFIG (OMAP2420_GPMC_BASE+0x50) |
| 48 | #define GPMC_CONFIG1_0 (OMAP2420_GPMC_BASE+0x60) |
| 49 | #define GPMC_CONFIG2_0 (OMAP2420_GPMC_BASE+0x64) |
| 50 | #define GPMC_CONFIG3_0 (OMAP2420_GPMC_BASE+0x68) |
| 51 | #define GPMC_CONFIG4_0 (OMAP2420_GPMC_BASE+0x6C) |
| 52 | #define GPMC_CONFIG5_0 (OMAP2420_GPMC_BASE+0x70) |
| 53 | #define GPMC_CONFIG7_0 (OMAP2420_GPMC_BASE+0x78) |
| 54 | #define GPMC_CONFIG1_1 (OMAP2420_GPMC_BASE+0x90) |
| 55 | #define GPMC_CONFIG2_1 (OMAP2420_GPMC_BASE+0x94) |
| 56 | #define GPMC_CONFIG3_1 (OMAP2420_GPMC_BASE+0x98) |
| 57 | #define GPMC_CONFIG4_1 (OMAP2420_GPMC_BASE+0x9C) |
| 58 | #define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) |
| 59 | #define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) |
| 60 | #define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) |
| 61 | |
| 62 | /* SMS */ |
| 63 | #define OMAP2420_SMS_BASE 0x68008000 |
| 64 | #define SMS_SYSCONFIG (OMAP2420_SMS_BASE+0x10) |
| 65 | |
| 66 | /* SDRC */ |
| 67 | #define OMAP2420_SDRC_BASE 0x68009000 |
| 68 | #define SDRC_SYSCONFIG (OMAP2420_SDRC_BASE+0x10) |
| 69 | #define SDRC_STATUS (OMAP2420_SDRC_BASE+0x14) |
| 70 | #define SDRC_SHARING (OMAP2420_SDRC_BASE+0x44) |
| 71 | #define SDRC_DLLA_CTRL (OMAP2420_SDRC_BASE+0x60) |
| 72 | #define SDRC_DLLB_CTRL (OMAP2420_SDRC_BASE+0x68) |
| 73 | #define SDRC_POWER (OMAP2420_SDRC_BASE+0x70) |
| 74 | #define SDRC_MCFG_0 (OMAP2420_SDRC_BASE+0x80) |
| 75 | #define SDRC_MR_0 (OMAP2420_SDRC_BASE+0x84) |
| 76 | #define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C) |
| 77 | #define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0) |
| 78 | #define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4) |
| 79 | #define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8) |
| 80 | #define SDRC_RFR_CTRL (OMAP2420_SDRC_BASE+0xA4) |
| 81 | #define SDRC_MANUAL_0 (OMAP2420_SDRC_BASE+0xA8) |
| 82 | #define OMAP2420_SDRC_CS0 0x80000000 |
| 83 | #define OMAP2420_SDRC_CS1 0xA0000000 |
| 84 | #define CMD_NOP 0x0 |
| 85 | #define CMD_PRECHARGE 0x1 |
| 86 | #define CMD_AUTOREFRESH 0x2 |
| 87 | #define CMD_ENTR_PWRDOWN 0x3 |
| 88 | #define CMD_EXIT_PWRDOWN 0x4 |
| 89 | #define CMD_ENTR_SRFRSH 0x5 |
| 90 | #define CMD_CKE_HIGH 0x6 |
| 91 | #define CMD_CKE_LOW 0x7 |
| 92 | #define SOFTRESET BIT1 |
| 93 | #define SMART_IDLE (0x2 << 3) |
| 94 | #define REF_ON_IDLE (0x1 << 6) |
| 95 | |
| 96 | |
| 97 | /* UART */ |
| 98 | #define OMAP2420_UART1 0x4806A000 |
| 99 | #define OMAP2420_UART2 0x4806C000 |
| 100 | #define OMAP2420_UART3 0x4806E000 |
| 101 | |
| 102 | /* General Purpose Timers */ |
| 103 | #define OMAP2420_GPT1 0x48028000 |
| 104 | #define OMAP2420_GPT2 0x4802A000 |
| 105 | #define OMAP2420_GPT3 0x48078000 |
| 106 | #define OMAP2420_GPT4 0x4807A000 |
| 107 | #define OMAP2420_GPT5 0x4807C000 |
| 108 | #define OMAP2420_GPT6 0x4807E000 |
| 109 | #define OMAP2420_GPT7 0x48080000 |
| 110 | #define OMAP2420_GPT8 0x48082000 |
| 111 | #define OMAP2420_GPT9 0x48084000 |
| 112 | #define OMAP2420_GPT10 0x48086000 |
| 113 | #define OMAP2420_GPT11 0x48088000 |
| 114 | #define OMAP2420_GPT12 0x4808A000 |
| 115 | |
| 116 | /* timer regs offsets (32 bit regs) */ |
| 117 | #define TIDR 0x0 /* r */ |
| 118 | #define TIOCP_CFG 0x10 /* rw */ |
| 119 | #define TISTAT 0x14 /* r */ |
| 120 | #define TISR 0x18 /* rw */ |
| 121 | #define TIER 0x1C /* rw */ |
| 122 | #define TWER 0x20 /* rw */ |
| 123 | #define TCLR 0x24 /* rw */ |
| 124 | #define TCRR 0x28 /* rw */ |
| 125 | #define TLDR 0x2C /* rw */ |
| 126 | #define TTGR 0x30 /* rw */ |
| 127 | #define TWPS 0x34 /* r */ |
| 128 | #define TMAR 0x38 /* rw */ |
| 129 | #define TCAR1 0x3c /* r */ |
| 130 | #define TSICR 0x40 /* rw */ |
| 131 | #define TCAR2 0x44 /* r */ |
| 132 | |
| 133 | /* WatchDog Timers (1 secure, 3 GP) */ |
| 134 | #define WD1_BASE 0x48020000 |
| 135 | #define WD2_BASE 0x48022000 |
| 136 | #define WD3_BASE 0x48024000 |
| 137 | #define WD4_BASE 0x48026000 |
| 138 | #define WWPS 0x34 /* r */ |
| 139 | #define WSPR 0x48 /* rw */ |
| 140 | #define WD_UNLOCK1 0xAAAA |
| 141 | #define WD_UNLOCK2 0x5555 |
| 142 | |
| 143 | /* PRCM */ |
| 144 | #define OMAP2420_CM_BASE 0x48008000 |
| 145 | #define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080) |
| 146 | #define CM_CLKSEL_MPU (OMAP2420_CM_BASE+0x140) |
| 147 | #define CM_FCLKEN1_CORE (OMAP2420_CM_BASE+0x200) |
| 148 | #define CM_FCLKEN2_CORE (OMAP2420_CM_BASE+0x204) |
| 149 | #define CM_ICLKEN1_CORE (OMAP2420_CM_BASE+0x210) |
| 150 | #define CM_ICLKEN2_CORE (OMAP2420_CM_BASE+0x214) |
| 151 | #define CM_CLKSEL1_CORE (OMAP2420_CM_BASE+0x240) |
| 152 | #define CM_CLKSEL_WKUP (OMAP2420_CM_BASE+0x440) |
| 153 | #define CM_CLKSEL2_CORE (OMAP2420_CM_BASE+0x244) |
| 154 | #define CM_CLKSEL_GFX (OMAP2420_CM_BASE+0x340) |
| 155 | #define PM_RSTCTRL_WKUP (OMAP2420_CM_BASE+0x450) |
| 156 | #define CM_CLKEN_PLL (OMAP2420_CM_BASE+0x500) |
| 157 | #define CM_IDLEST_CKGEN (OMAP2420_CM_BASE+0x520) |
| 158 | #define CM_CLKSEL1_PLL (OMAP2420_CM_BASE+0x540) |
| 159 | #define CM_CLKSEL2_PLL (OMAP2420_CM_BASE+0x544) |
| 160 | #define CM_CLKSEL_DSP (OMAP2420_CM_BASE+0x840) |
| 161 | |
| 162 | /* |
| 163 | * H4 specific Section |
| 164 | */ |
| 165 | |
| 166 | /* |
| 167 | * The 2420's chip selects are programmable. The mask ROM |
| 168 | * does configure CS0 to 0x08000000 before dispatch. So, if |
| 169 | * you want your code to live below that address, you have to |
| 170 | * be prepared to jump though hoops, to reset the base address. |
| 171 | */ |
| 172 | #if defined(CONFIG_OMAP2420H4) |
| 173 | /* GPMC */ |
| 174 | #ifdef CONFIG_VIRTIO_A /* Pre version B */ |
| 175 | # define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ |
| 176 | # define H4_CS1_BASE 0x04000000 /* debug board */ |
| 177 | # define H4_CS2_BASE 0x0A000000 /* wifi board */ |
| 178 | #else |
| 179 | # define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */ |
| 180 | # define H4_CS1_BASE 0x08000000 /* debug board */ |
| 181 | # define H4_CS2_BASE 0x0A000000 /* wifi board */ |
| 182 | #endif |
| 183 | |
| 184 | /* base address for indirect vectors (internal boot mode) */ |
| 185 | #define SRAM_OFFSET0 0x40000000 |
| 186 | #define SRAM_OFFSET1 0x00200000 |
| 187 | #define SRAM_OFFSET2 0x0000F800 |
| 188 | #define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) |
| 189 | |
| 190 | #define LOW_LEVEL_SRAM_STACK 0x4020FFFC |
| 191 | |
| 192 | #define PERIFERAL_PORT_BASE 0x480FE003 |
| 193 | |
| 194 | /* FPGA on Debug board.*/ |
| 195 | #define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) |
| 196 | #define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) |
| 197 | #endif /* endif CONFIG_2420H4 */ |
| 198 | |
| 199 | #endif |
| 200 | |