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wdenk074cff02004-02-24 00:16:43 +00001/*
2 * Startup Code for S3C44B0 CPU-core
3 *
4 * (C) Copyright 2004
5 * DAVE Srl
6 *
7 * http://www.dave-tech.it
8 * http://www.wawnet.biz
9 * mailto:info@wawnet.biz
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30
31#include <config.h>
32#include <version.h>
33
34
35/*
36 * Jump vector table
37 */
38
39
40.globl _start
41_start: b reset
42 add pc, pc, #0x0c000000
43 add pc, pc, #0x0c000000
44 add pc, pc, #0x0c000000
45 add pc, pc, #0x0c000000
46 add pc, pc, #0x0c000000
47 add pc, pc, #0x0c000000
48 add pc, pc, #0x0c000000
49
50 .balignl 16,0xdeadbeef
51
52
53/*
54 *************************************************************************
55 *
56 * Startup Code (reset vector)
57 *
58 * do important init only if we don't start from memory!
59 * relocate u-boot to ram
60 * setup stack
61 * jump to second stage
62 *
63 *************************************************************************
64 */
65
66_TEXT_BASE:
67 .word TEXT_BASE
68
69.globl _armboot_start
70_armboot_start:
71 .word _start
72
73/*
wdenk42dfe7a2004-03-14 22:25:36 +000074 * These are defined in the board-specific linker script.
wdenk074cff02004-02-24 00:16:43 +000075 */
wdenk42dfe7a2004-03-14 22:25:36 +000076.globl _bss_start
77_bss_start:
78 .word __bss_start
79
80.globl _bss_end
81_bss_end:
82 .word _end
wdenk074cff02004-02-24 00:16:43 +000083
84#ifdef CONFIG_USE_IRQ
85/* IRQ stack memory (calculated at run-time) */
86.globl IRQ_STACK_START
87IRQ_STACK_START:
88 .word 0x0badc0de
89
90/* IRQ stack memory (calculated at run-time) */
91.globl FIQ_STACK_START
92FIQ_STACK_START:
93 .word 0x0badc0de
94#endif
95
96
97/*
98 * the actual reset code
99 */
100
101reset:
102 /*
103 * set the cpu to SVC32 mode
104 */
105 mrs r0,cpsr
106 bic r0,r0,#0x1f
107 orr r0,r0,#0x13
108 msr cpsr,r0
109
110 /*
111 * we do sys-critical inits only at reboot,
112 * not when booting from ram!
113 */
114
115#ifdef CONFIG_INIT_CRITICAL
116 bl cpu_init_crit
117 /*
118 * before relocating, we have to setup RAM timing
119 * because memory timing is board-dependend, you will
120 * find a memsetup.S in your board directory.
121 */
122 bl memsetup
123#endif
124
125relocate: /* relocate U-Boot to RAM */
126 adr r0, _start /* r0 <- current position of code */
127 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
128 cmp r0, r1 /* don't reloc during debug */
129 beq stack_setup
130
131 ldr r2, _armboot_start
wdenk42dfe7a2004-03-14 22:25:36 +0000132 ldr r3, _bss_start
wdenk074cff02004-02-24 00:16:43 +0000133 sub r2, r3, r2 /* r2 <- size of armboot */
134 add r2, r0, r2 /* r2 <- source end address */
135
136copy_loop:
137 ldmia r0!, {r3-r10} /* copy from source address [r0] */
138 stmia r1!, {r3-r10} /* copy to target address [r1] */
139 cmp r0, r2 /* until source end addreee [r2] */
140 ble copy_loop
141
142/*
143 now copy to sram the interrupt vector
144*/
145 adr r0, real_vectors
146 add r2, r0, #1024
147 ldr r1, =0x0c000000
148 add r1, r1, #0x08
149vector_copy_loop:
150 ldmia r0!, {r3-r10}
151 stmia r1!, {r3-r10}
152 cmp r0, r2
153 ble vector_copy_loop
154
155 /* Set up the stack */
156stack_setup:
157 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
158 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
159 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
160#ifdef CONFIG_USE_IRQ
161 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
162#endif
163 sub sp, r0, #12 /* leave 3 words for abort-stack */
164
165 ldr pc, _start_armboot
166
167_start_armboot: .word start_armboot
168
169
170/*
171 *************************************************************************
172 *
173 * CPU_init_critical registers
174 *
175 * setup important registers
176 * setup memory timing
177 *
178 *************************************************************************
179 */
180
181#define INTCON (0x01c00000+0x200000)
182#define INTMSK (0x01c00000+0x20000c)
183#define LOCKTIME (0x01c00000+0x18000c)
184#define PLLCON (0x01c00000+0x180000)
185#define CLKCON (0x01c00000+0x180004)
186#define WTCON (0x01c00000+0x130000)
187cpu_init_crit:
188 /* disable watch dog */
189 ldr r0, =WTCON
190 ldr r1, =0x0
191 str r1, [r0]
192
193 /*
194 * mask all IRQs by clearing all bits in the INTMRs
195 */
196 ldr r1,=INTMSK
197 ldr r0, =0x03fffeff
198 str r0, [r1]
199
200 ldr r1, =INTCON
201 ldr r0, =0x05
202 str r0, [r1]
203
204 /* Set Clock Control Register */
205 ldr r1, =LOCKTIME
206 ldrb r0, =800
207 strb r0, [r1]
208
209 ldr r1, =PLLCON
210
211#if CONFIG_S3C44B0_CLOCK_SPEED==66
212 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
213#elif CONFIG_S3C44B0_CLOCK_SPEED==75
214 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
215#else
216# error CONFIG_S3C44B0_CLOCK_SPEED undefined
217#endif
218
219 str r0, [r1]
220
221 ldr r1,=CLKCON
222 ldr r0, =0x7ff8
223 str r0, [r1]
224
225 mov pc, lr
226
227
228/*************************************************/
229/* interrupt vectors */
230/*************************************************/
231real_vectors:
232 b reset
233 b undefined_instruction
234 b software_interrupt
235 b prefetch_abort
236 b data_abort
237 b not_used
238 b irq
239 b fiq
240
241/*************************************************/
242
243undefined_instruction:
244 mov r6, #3
245 b reset
246
247software_interrupt:
248 mov r6, #4
249 b reset
250
251prefetch_abort:
252 mov r6, #5
253 b reset
254
255data_abort:
256 mov r6, #6
257 b reset
258
259not_used:
260 /* we *should* never reach this */
261 mov r6, #7
262 b reset
263
264irq:
265 mov r6, #8
266 b reset
267
268fiq:
269 mov r6, #9
270 b reset