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wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk97d80fc2004-06-09 00:34:46 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <watchdog.h>
30#include <command.h>
31#include <asm/cache.h>
32
33/* ------------------------------------------------------------------------- */
34
35int checkcpu (void)
36{
wdenk97d80fc2004-06-09 00:34:46 +000037 sys_info_t sysinfo;
38 uint lcrr; /* local bus clock ratio register */
39 uint clkdiv; /* clock divider portion of lcrr */
40 uint pvr, svr;
41 uint ver;
42 uint major, minor;
wdenk42d1f032003-10-15 23:53:47 +000043
wdenk97d80fc2004-06-09 00:34:46 +000044 puts("Freescale PowerPC\n");
45
46 pvr = get_pvr();
47 ver = PVR_VER(pvr);
48 major = PVR_MAJ(pvr);
49 minor = PVR_MIN(pvr);
50
51 printf(" Core: ");
52 switch (ver) {
53 case PVR_VER(PVR_85xx):
54 puts("E500");
55 break;
wdenk42d1f032003-10-15 23:53:47 +000056 default:
wdenk97d80fc2004-06-09 00:34:46 +000057 puts("Unknown");
58 break;
59 }
60 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
61
62 svr = get_svr();
63 ver = SVR_VER(svr);
64 major = SVR_MAJ(svr);
65 minor = SVR_MIN(svr);
66
67 puts(" System: ");
68 switch (ver) {
69 case SVR_8540:
70 puts("8540");
71 break;
72 case SVR_8541:
73 puts("8541");
74 break;
75 case SVR_8555:
76 puts("8555");
77 break;
78 case SVR_8560:
79 puts("8560");
80 break;
81 default:
82 puts("Unknown");
wdenk42d1f032003-10-15 23:53:47 +000083 break;
84 }
wdenk97d80fc2004-06-09 00:34:46 +000085 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
wdenk42d1f032003-10-15 23:53:47 +000086
wdenk97d80fc2004-06-09 00:34:46 +000087 get_sys_info(&sysinfo);
88
89 puts(" Clocks: ");
90 printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
91 printf("CCB:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
92 printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
93
94#if defined(CFG_LBC_LCRR)
95 lcrr = CFG_LBC_LCRR;
96#else
97 {
98 volatile immap_t *immap = (immap_t *)CFG_IMMR;
99 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
100
101 lcrr = lbc->lcrr;
102 }
103#endif
104 clkdiv = lcrr & 0x0f;
105 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
106 printf("LBC:%4lu MHz\n",
107 sysinfo.freqSystemBus / 1000000 / clkdiv);
108 } else {
109 printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
110 }
111
112 if (ver == SVR_8560) {
113 printf(" CPM: %lu Mhz\n",
114 sysinfo.freqSystemBus / 1000000);
115 }
116
117 puts(" L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
wdenk42d1f032003-10-15 23:53:47 +0000118
119 return 0;
120}
121
122
123/* ------------------------------------------------------------------------- */
124
125int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
126{
127 /*
128 * Initiate hard reset in debug control register DBCR0
129 * Make sure MSR[DE] = 1
130 */
wdenk97d80fc2004-06-09 00:34:46 +0000131 unsigned long val;
132
133 val = mfspr(DBCR0);
134 val |= 0x70000000;
135 mtspr(DBCR0,val);
136
wdenk42d1f032003-10-15 23:53:47 +0000137 return 1;
138}
139
140
141/*
142 * Get timebase clock frequency
143 */
144unsigned long get_tbclk (void)
145{
146
147 sys_info_t sys_info;
148
149 get_sys_info(&sys_info);
150 return ((sys_info.freqSystemBus + 3L) / 4L);
151}
152
153
154#if defined(CONFIG_WATCHDOG)
155void
156watchdog_reset(void)
157{
158 int re_enable = disable_interrupts();
159 reset_85xx_watchdog();
160 if (re_enable) enable_interrupts();
161}
162
163void
164reset_85xx_watchdog(void)
165{
166 /*
167 * Clear TSR(WIS) bit by writing 1
168 */
169 unsigned long val;
170 val = mfspr(tsr);
171 val |= 0x40000000;
172 mtspr(tsr, val);
173}
174#endif /* CONFIG_WATCHDOG */
175
176#if defined(CONFIG_DDR_ECC)
wdenk42d1f032003-10-15 23:53:47 +0000177void dma_init(void) {
178 volatile immap_t *immap = (immap_t *)CFG_IMMR;
179 volatile ccsr_dma_t *dma = &immap->im_dma;
180
181 dma->satr0 = 0x02c40000;
182 dma->datr0 = 0x02c40000;
183 asm("sync; isync; msync");
184 return;
185}
186
187uint dma_check(void) {
188 volatile immap_t *immap = (immap_t *)CFG_IMMR;
189 volatile ccsr_dma_t *dma = &immap->im_dma;
190 volatile uint status = dma->sr0;
191
192 /* While the channel is busy, spin */
193 while((status & 4) == 4) {
194 status = dma->sr0;
195 }
196
197 if (status != 0) {
198 printf ("DMA Error: status = %x\n", status);
199 }
200 return status;
201}
202
203int dma_xfer(void *dest, uint count, void *src) {
204 volatile immap_t *immap = (immap_t *)CFG_IMMR;
205 volatile ccsr_dma_t *dma = &immap->im_dma;
206
207 dma->dar0 = (uint) dest;
208 dma->sar0 = (uint) src;
209 dma->bcr0 = count;
210 dma->mr0 = 0xf000004;
211 asm("sync;isync;msync");
212 dma->mr0 = 0xf000005;
213 asm("sync;isync;msync");
214 return dma_check();
215}
216#endif