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wdenk47d1a6e2002-11-03 00:01:44 +00001/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2001 Josh Huber <huber@mclx.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/* U-Boot - Startup Code for PowerPC based Embedded Boards
27 *
28 *
29 * The processor starts at 0xfff00100 and the code is executed
30 * from flash. The code is organized to be at an other address
31 * in memory, but as long we don't jump around before relocating.
32 * board_init lies at a quite high address and when the cpu has
33 * jumped there, everything is ok.
34 */
35#include <config.h>
36#include <74xx_7xx.h>
37#include <version.h>
38
39#include <ppc_asm.tmpl>
40#include <ppc_defs.h>
41
42#include <asm/cache.h>
43#include <asm/mmu.h>
44
wdenk3a473b22004-01-03 00:43:19 +000045#if !defined(CONFIG_DB64360) && \
stroese0912e482004-12-16 18:10:54 +000046 !defined(CONFIG_DB64460) && \
47 !defined(CONFIG_CPCI750)
wdenk47d1a6e2002-11-03 00:01:44 +000048#include <galileo/gt64260R.h>
wdenk3a473b22004-01-03 00:43:19 +000049#endif
wdenk47d1a6e2002-11-03 00:01:44 +000050
51#ifndef CONFIG_IDENT_STRING
52#define CONFIG_IDENT_STRING ""
53#endif
54
55/* We don't want the MMU yet.
56*/
57#undef MSR_KERNEL
58/* Machine Check and Recoverable Interr. */
59#define MSR_KERNEL ( MSR_ME | MSR_RI )
60
61/*
62 * Set up GOT: Global Offset Table
63 *
64 * Use r14 to access the GOT
65 */
66 START_GOT
67 GOT_ENTRY(_GOT2_TABLE_)
68 GOT_ENTRY(_FIXUP_TABLE_)
69
70 GOT_ENTRY(_start)
71 GOT_ENTRY(_start_of_vectors)
72 GOT_ENTRY(_end_of_vectors)
73 GOT_ENTRY(transfer_to_handler)
74
wdenk3b57fe02003-05-30 12:48:29 +000075 GOT_ENTRY(__init_end)
wdenk47d1a6e2002-11-03 00:01:44 +000076 GOT_ENTRY(_end)
wdenk5d232d02003-05-22 22:52:13 +000077 GOT_ENTRY(__bss_start)
wdenk47d1a6e2002-11-03 00:01:44 +000078 END_GOT
79
80/*
81 * r3 - 1st arg to board_init(): IMMP pointer
82 * r4 - 2nd arg to board_init(): boot flag
83 */
84 .text
85 .long 0x27051956 /* U-Boot Magic Number */
86 .globl version_string
87version_string:
88 .ascii U_BOOT_VERSION
89 .ascii " (", __DATE__, " - ", __TIME__, ")"
90 .ascii CONFIG_IDENT_STRING, "\0"
91
92 . = EXC_OFF_SYS_RESET
93 .globl _start
94_start:
95 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
96 b boot_cold
97 sync
98
99 . = EXC_OFF_SYS_RESET + 0x10
100
101 .globl _start_warm
102_start_warm:
103 li r21, BOOTFLAG_WARM /* Software reboot */
104 b boot_warm
105 sync
106
107 /* the boot code is located below the exception table */
108
109 .globl _start_of_vectors
110_start_of_vectors:
111
112/* Machine check */
113 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
114
115/* Data Storage exception. "Never" generated on the 860. */
116 STD_EXCEPTION(0x300, DataStorage, UnknownException)
117
118/* Instruction Storage exception. "Never" generated on the 860. */
119 STD_EXCEPTION(0x400, InstStorage, UnknownException)
120
121/* External Interrupt exception. */
122 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
123
124/* Alignment exception. */
125 . = 0x600
126Alignment:
127 EXCEPTION_PROLOG
128 mfspr r4,DAR
129 stw r4,_DAR(r21)
130 mfspr r5,DSISR
131 stw r5,_DSISR(r21)
132 addi r3,r1,STACK_FRAME_OVERHEAD
133 li r20,MSR_KERNEL
134 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
135 lwz r6,GOT(transfer_to_handler)
136 mtlr r6
137 blrl
138.L_Alignment:
139 .long AlignmentException - _start + EXC_OFF_SYS_RESET
140 .long int_return - _start + EXC_OFF_SYS_RESET
141
142/* Program check exception */
143 . = 0x700
144ProgramCheck:
145 EXCEPTION_PROLOG
146 addi r3,r1,STACK_FRAME_OVERHEAD
147 li r20,MSR_KERNEL
148 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
149 lwz r6,GOT(transfer_to_handler)
150 mtlr r6
151 blrl
152.L_ProgramCheck:
153 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
154 .long int_return - _start + EXC_OFF_SYS_RESET
155
156 /* No FPU on MPC8xx. This exception is not supposed to happen.
157 */
158 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
159
160 /* I guess we could implement decrementer, and may have
161 * to someday for timekeeping.
162 */
163 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
164 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
165 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
wdenk27b207f2003-07-24 23:38:38 +0000166 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
wdenk47d1a6e2002-11-03 00:01:44 +0000167 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
168
169 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
170 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
171
wdenk8bde7f72003-06-27 21:31:46 +0000172 /*
173 * On the MPC8xx, this is a software emulation interrupt. It
174 * occurs for all unimplemented and illegal instructions.
wdenk47d1a6e2002-11-03 00:01:44 +0000175 */
176 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
177
178 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
179 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
180 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
181 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
182
183 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
184 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
185 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
186 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
187 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
188 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
189 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
190
191 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
192 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
193 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
194 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
195
196 .globl _end_of_vectors
197_end_of_vectors:
198
199 . = 0x2000
200
201boot_cold:
202boot_warm:
203 /* disable everything */
204 li r0, 0
205 mtspr HID0, r0
206 sync
207 mtmsr 0
208 bl invalidate_bats
209 sync
210
211#ifdef CFG_L2
212 /* init the L2 cache */
213 addis r3, r0, L2_INIT@h
214 ori r3, r3, L2_INIT@l
215 sync
216 mtspr l2cr, r3
217#endif
218#if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
219 .long 0x7e00066c
220 /*
wdenk8bde7f72003-06-27 21:31:46 +0000221 * dssall instruction, gas doesn't have it yet
222 * ...for altivec, data stream stop all this probably
223 * isn't needed unless we warm (software) reboot U-Boot
wdenk47d1a6e2002-11-03 00:01:44 +0000224 */
225#endif
226
227#ifdef CFG_L2
228 /* invalidate the L2 cache */
229 bl l2cache_invalidate
230 sync
231#endif
232#ifdef CFG_BOARD_ASM_INIT
233 /* do early init */
234 bl board_asm_init
235#endif
236
237 /*
238 * Calculate absolute address in FLASH and jump there
239 *------------------------------------------------------*/
240 lis r3, CFG_MONITOR_BASE@h
241 ori r3, r3, CFG_MONITOR_BASE@l
242 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
243 mtlr r3
244 blr
245
246in_flash:
247 /* let the C-code set up the rest */
248 /* */
249 /* Be careful to keep code relocatable ! */
250 /*------------------------------------------------------*/
251
252 /* perform low-level init */
253 /* sdram init, galileo init, etc */
254 /* r3: NHR bit from HID0 */
255
256 /* setup the bats */
257 bl setup_bats
258 sync
259
260 /*
261 * Cache must be enabled here for stack-in-cache trick.
262 * This means we need to enable the BATS.
263 * This means:
wdenk8bde7f72003-06-27 21:31:46 +0000264 * 1) for the EVB, original gt regs need to be mapped
wdenk47d1a6e2002-11-03 00:01:44 +0000265 * 2) need to have an IBAT for the 0xf region,
266 * we are running there!
wdenk8bde7f72003-06-27 21:31:46 +0000267 * Cache should be turned on after BATs, since by default
268 * everything is write-through.
269 * The init-mem BAT can be reused after reloc. The old
270 * gt-regs BAT can be reused after board_init_f calls
wdenkc837dcb2004-01-20 23:12:12 +0000271 * board_early_init_f (EVB only).
wdenk8bde7f72003-06-27 21:31:46 +0000272 */
wdenk47d1a6e2002-11-03 00:01:44 +0000273#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC)
274 /* enable address translation */
275 bl enable_addr_trans
276 sync
277
278 /* enable and invalidate the data cache */
279 bl l1dcache_enable
280 sync
281#endif
282#ifdef CFG_INIT_RAM_LOCK
283 bl lock_ram_in_cache
284 sync
285#endif
286
287 /* set up the stack pointer in our newly created
288 * cache-ram (r1) */
289 lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
290 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
291
292 li r0, 0 /* Make room for stack frame header and */
293 stwu r0, -4(r1) /* clear final stack frame so that */
294 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
295
296 GET_GOT /* initialize GOT access */
297
298 /* run low-level CPU init code (from Flash) */
299 bl cpu_init_f
300 sync
301
302 mr r3, r21
303
304 /* r3: BOOTFLAG */
305 /* run 1st part of board init code (from Flash) */
306 bl board_init_f
307 sync
308
309 /* NOTREACHED */
310
311 .globl invalidate_bats
312invalidate_bats:
313 /* invalidate BATs */
314 mtspr IBAT0U, r0
315 mtspr IBAT1U, r0
316 mtspr IBAT2U, r0
317 mtspr IBAT3U, r0
wdenk72755c72003-06-20 23:10:58 +0000318#ifdef CONFIG_750FX
319 mtspr IBAT4U, r0
320 mtspr IBAT5U, r0
321 mtspr IBAT6U, r0
322 mtspr IBAT7U, r0
323#endif
wdenk47d1a6e2002-11-03 00:01:44 +0000324 isync
325 mtspr DBAT0U, r0
326 mtspr DBAT1U, r0
327 mtspr DBAT2U, r0
328 mtspr DBAT3U, r0
wdenk72755c72003-06-20 23:10:58 +0000329#ifdef CONFIG_750FX
wdenk8bde7f72003-06-27 21:31:46 +0000330 mtspr DBAT4U, r0
331 mtspr DBAT5U, r0
332 mtspr DBAT6U, r0
333 mtspr DBAT7U, r0
wdenk72755c72003-06-20 23:10:58 +0000334#endif
wdenk47d1a6e2002-11-03 00:01:44 +0000335 isync
336 sync
337 blr
338
339 /* setup_bats - set them up to some initial state */
340 .globl setup_bats
341setup_bats:
342 addis r0, r0, 0x0000
343
344 /* IBAT 0 */
345 addis r4, r0, CFG_IBAT0L@h
346 ori r4, r4, CFG_IBAT0L@l
347 addis r3, r0, CFG_IBAT0U@h
348 ori r3, r3, CFG_IBAT0U@l
349 mtspr IBAT0L, r4
350 mtspr IBAT0U, r3
351 isync
352
353 /* DBAT 0 */
354 addis r4, r0, CFG_DBAT0L@h
355 ori r4, r4, CFG_DBAT0L@l
356 addis r3, r0, CFG_DBAT0U@h
357 ori r3, r3, CFG_DBAT0U@l
358 mtspr DBAT0L, r4
359 mtspr DBAT0U, r3
360 isync
361
362 /* IBAT 1 */
363 addis r4, r0, CFG_IBAT1L@h
364 ori r4, r4, CFG_IBAT1L@l
365 addis r3, r0, CFG_IBAT1U@h
366 ori r3, r3, CFG_IBAT1U@l
367 mtspr IBAT1L, r4
368 mtspr IBAT1U, r3
369 isync
370
371 /* DBAT 1 */
372 addis r4, r0, CFG_DBAT1L@h
373 ori r4, r4, CFG_DBAT1L@l
374 addis r3, r0, CFG_DBAT1U@h
375 ori r3, r3, CFG_DBAT1U@l
376 mtspr DBAT1L, r4
377 mtspr DBAT1U, r3
378 isync
379
380 /* IBAT 2 */
381 addis r4, r0, CFG_IBAT2L@h
382 ori r4, r4, CFG_IBAT2L@l
383 addis r3, r0, CFG_IBAT2U@h
384 ori r3, r3, CFG_IBAT2U@l
385 mtspr IBAT2L, r4
386 mtspr IBAT2U, r3
387 isync
388
389 /* DBAT 2 */
390 addis r4, r0, CFG_DBAT2L@h
391 ori r4, r4, CFG_DBAT2L@l
392 addis r3, r0, CFG_DBAT2U@h
393 ori r3, r3, CFG_DBAT2U@l
394 mtspr DBAT2L, r4
395 mtspr DBAT2U, r3
396 isync
397
398 /* IBAT 3 */
399 addis r4, r0, CFG_IBAT3L@h
400 ori r4, r4, CFG_IBAT3L@l
401 addis r3, r0, CFG_IBAT3U@h
402 ori r3, r3, CFG_IBAT3U@l
403 mtspr IBAT3L, r4
404 mtspr IBAT3U, r3
405 isync
406
407 /* DBAT 3 */
408 addis r4, r0, CFG_DBAT3L@h
409 ori r4, r4, CFG_DBAT3L@l
410 addis r3, r0, CFG_DBAT3U@h
411 ori r3, r3, CFG_DBAT3U@l
412 mtspr DBAT3L, r4
413 mtspr DBAT3U, r3
414 isync
415
wdenk72755c72003-06-20 23:10:58 +0000416#ifdef CONFIG_750FX
417 /* IBAT 4 */
wdenk8bde7f72003-06-27 21:31:46 +0000418 addis r4, r0, CFG_IBAT4L@h
419 ori r4, r4, CFG_IBAT4L@l
420 addis r3, r0, CFG_IBAT4U@h
421 ori r3, r3, CFG_IBAT4U@l
422 mtspr IBAT4L, r4
423 mtspr IBAT4U, r3
424 isync
wdenk72755c72003-06-20 23:10:58 +0000425
426 /* DBAT 4 */
wdenk8bde7f72003-06-27 21:31:46 +0000427 addis r4, r0, CFG_DBAT4L@h
428 ori r4, r4, CFG_DBAT4L@l
429 addis r3, r0, CFG_DBAT4U@h
430 ori r3, r3, CFG_DBAT4U@l
431 mtspr DBAT4L, r4
432 mtspr DBAT4U, r3
433 isync
wdenk72755c72003-06-20 23:10:58 +0000434
wdenk8bde7f72003-06-27 21:31:46 +0000435 /* IBAT 5 */
436 addis r4, r0, CFG_IBAT5L@h
437 ori r4, r4, CFG_IBAT5L@l
438 addis r3, r0, CFG_IBAT5U@h
439 ori r3, r3, CFG_IBAT5U@l
440 mtspr IBAT5L, r4
441 mtspr IBAT5U, r3
442 isync
wdenk72755c72003-06-20 23:10:58 +0000443
444 /* DBAT 5 */
wdenk8bde7f72003-06-27 21:31:46 +0000445 addis r4, r0, CFG_DBAT5L@h
446 ori r4, r4, CFG_DBAT5L@l
447 addis r3, r0, CFG_DBAT5U@h
448 ori r3, r3, CFG_DBAT5U@l
449 mtspr DBAT5L, r4
450 mtspr DBAT5U, r3
451 isync
wdenk72755c72003-06-20 23:10:58 +0000452
wdenk8bde7f72003-06-27 21:31:46 +0000453 /* IBAT 6 */
454 addis r4, r0, CFG_IBAT6L@h
455 ori r4, r4, CFG_IBAT6L@l
456 addis r3, r0, CFG_IBAT6U@h
457 ori r3, r3, CFG_IBAT6U@l
458 mtspr IBAT6L, r4
459 mtspr IBAT6U, r3
460 isync
wdenk72755c72003-06-20 23:10:58 +0000461
462 /* DBAT 6 */
wdenk8bde7f72003-06-27 21:31:46 +0000463 addis r4, r0, CFG_DBAT6L@h
464 ori r4, r4, CFG_DBAT6L@l
465 addis r3, r0, CFG_DBAT6U@h
466 ori r3, r3, CFG_DBAT6U@l
467 mtspr DBAT6L, r4
468 mtspr DBAT6U, r3
469 isync
wdenk72755c72003-06-20 23:10:58 +0000470
wdenk8bde7f72003-06-27 21:31:46 +0000471 /* IBAT 7 */
472 addis r4, r0, CFG_IBAT7L@h
473 ori r4, r4, CFG_IBAT7L@l
474 addis r3, r0, CFG_IBAT7U@h
475 ori r3, r3, CFG_IBAT7U@l
476 mtspr IBAT7L, r4
477 mtspr IBAT7U, r3
478 isync
wdenk72755c72003-06-20 23:10:58 +0000479
480 /* DBAT 7 */
wdenk8bde7f72003-06-27 21:31:46 +0000481 addis r4, r0, CFG_DBAT7L@h
482 ori r4, r4, CFG_DBAT7L@l
483 addis r3, r0, CFG_DBAT7U@h
484 ori r3, r3, CFG_DBAT7U@l
485 mtspr DBAT7L, r4
486 mtspr DBAT7U, r3
487 isync
wdenk72755c72003-06-20 23:10:58 +0000488#endif
489
wdenk47d1a6e2002-11-03 00:01:44 +0000490 /* bats are done, now invalidate the TLBs */
491
492 addis r3, 0, 0x0000
493 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
494
495 isync
496
497tlblp:
498 tlbie r3
499 sync
500 addi r3, r3, 0x1000
501 cmp 0, 0, r3, r5
502 blt tlblp
503
504 blr
505
506 .globl enable_addr_trans
507enable_addr_trans:
508 /* enable address translation */
509 mfmsr r5
510 ori r5, r5, (MSR_IR | MSR_DR)
511 mtmsr r5
512 isync
513 blr
514
515 .globl disable_addr_trans
516disable_addr_trans:
517 /* disable address translation */
518 mflr r4
519 mfmsr r3
520 andi. r0, r3, (MSR_IR | MSR_DR)
521 beqlr
522 andc r3, r3, r0
523 mtspr SRR0, r4
524 mtspr SRR1, r3
525 rfi
526
527/*
528 * This code finishes saving the registers to the exception frame
529 * and jumps to the appropriate handler for the exception.
530 * Register r21 is pointer into trap frame, r1 has new stack pointer.
531 */
532 .globl transfer_to_handler
533transfer_to_handler:
534 stw r22,_NIP(r21)
535 lis r22,MSR_POW@h
536 andc r23,r23,r22
537 stw r23,_MSR(r21)
538 SAVE_GPR(7, r21)
539 SAVE_4GPRS(8, r21)
540 SAVE_8GPRS(12, r21)
541 SAVE_8GPRS(24, r21)
542 mflr r23
543 andi. r24,r23,0x3f00 /* get vector offset */
544 stw r24,TRAP(r21)
545 li r22,0
546 stw r22,RESULT(r21)
547 mtspr SPRG2,r22 /* r1 is now kernel sp */
548 lwz r24,0(r23) /* virtual address of handler */
549 lwz r23,4(r23) /* where to go when done */
550 mtspr SRR0,r24
551 mtspr SRR1,r20
552 mtlr r23
553 SYNC
554 rfi /* jump to handler, enable MMU */
555
556int_return:
557 mfmsr r28 /* Disable interrupts */
558 li r4,0
559 ori r4,r4,MSR_EE
560 andc r28,r28,r4
561 SYNC /* Some chip revs need this... */
562 mtmsr r28
563 SYNC
564 lwz r2,_CTR(r1)
565 lwz r0,_LINK(r1)
566 mtctr r2
567 mtlr r0
568 lwz r2,_XER(r1)
569 lwz r0,_CCR(r1)
570 mtspr XER,r2
571 mtcrf 0xFF,r0
572 REST_10GPRS(3, r1)
573 REST_10GPRS(13, r1)
574 REST_8GPRS(23, r1)
575 REST_GPR(31, r1)
576 lwz r2,_NIP(r1) /* Restore environment */
577 lwz r0,_MSR(r1)
578 mtspr SRR0,r2
579 mtspr SRR1,r0
580 lwz r0,GPR0(r1)
581 lwz r2,GPR2(r1)
582 lwz r1,GPR1(r1)
583 SYNC
584 rfi
585
586 .globl dc_read
587dc_read:
588 blr
589
590 .globl get_pvr
591get_pvr:
592 mfspr r3, PVR
593 blr
594
595/*-----------------------------------------------------------------------*/
596/*
597 * void relocate_code (addr_sp, gd, addr_moni)
598 *
599 * This "function" does not return, instead it continues in RAM
600 * after relocating the monitor code.
601 *
602 * r3 = dest
603 * r4 = src
604 * r5 = length in bytes
605 * r6 = cachelinesize
606 */
607 .globl relocate_code
608relocate_code:
609 mr r1, r3 /* Set new stack pointer */
610 mr r9, r4 /* Save copy of Global Data pointer */
611 mr r10, r5 /* Save copy of Destination Address */
612
613 mr r3, r5 /* Destination Address */
614 lis r4, CFG_MONITOR_BASE@h /* Source Address */
615 ori r4, r4, CFG_MONITOR_BASE@l
wdenk3b57fe02003-05-30 12:48:29 +0000616 lwz r5, GOT(__init_end)
617 sub r5, r5, r4
wdenk47d1a6e2002-11-03 00:01:44 +0000618 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
619
620 /*
621 * Fix GOT pointer:
622 *
623 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
624 *
625 * Offset:
626 */
627 sub r15, r10, r4
628
629 /* First our own GOT */
630 add r14, r14, r15
631 /* then the one used by the C code */
632 add r30, r30, r15
633
634 /*
635 * Now relocate code
636 */
637#ifdef CONFIG_ECC
638 bl board_relocate_rom
639 sync
640 mr r3, r10 /* Destination Address */
641 lis r4, CFG_MONITOR_BASE@h /* Source Address */
642 ori r4, r4, CFG_MONITOR_BASE@l
wdenk3b57fe02003-05-30 12:48:29 +0000643 lwz r5, GOT(__init_end)
644 sub r5, r5, r4
wdenk47d1a6e2002-11-03 00:01:44 +0000645 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
646#else
647 cmplw cr1,r3,r4
648 addi r0,r5,3
649 srwi. r0,r0,2
650 beq cr1,4f /* In place copy is not necessary */
651 beq 7f /* Protect against 0 count */
652 mtctr r0
653 bge cr1,2f
654
655 la r8,-4(r4)
656 la r7,-4(r3)
6571: lwzu r0,4(r8)
658 stwu r0,4(r7)
659 bdnz 1b
660 b 4f
661
6622: slwi r0,r0,2
663 add r8,r4,r0
664 add r7,r3,r0
6653: lwzu r0,-4(r8)
666 stwu r0,-4(r7)
667 bdnz 3b
668#endif
669/*
670 * Now flush the cache: note that we must start from a cache aligned
671 * address. Otherwise we might miss one cache line.
672 */
6734: cmpwi r6,0
674 add r5,r3,r5
675 beq 7f /* Always flush prefetch queue in any case */
676 subi r0,r6,1
677 andc r3,r3,r0
678 mr r4,r3
6795: dcbst 0,r4
680 add r4,r4,r6
681 cmplw r4,r5
682 blt 5b
683 sync /* Wait for all dcbst to complete on bus */
684 mr r4,r3
6856: icbi 0,r4
686 add r4,r4,r6
687 cmplw r4,r5
688 blt 6b
6897: sync /* Wait for all icbi to complete on bus */
690 isync
691
692/*
693 * We are done. Do not return, instead branch to second part of board
694 * initialization, now running from RAM.
695 */
696 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
697 mtlr r0
698 blr
699
700in_ram:
701#ifdef CONFIG_ECC
702 bl board_init_ecc
703#endif
704 /*
705 * Relocation Function, r14 point to got2+0x8000
706 *
wdenk8bde7f72003-06-27 21:31:46 +0000707 * Adjust got2 pointers, no need to check for 0, this code
708 * already puts a few entries in the table.
wdenk47d1a6e2002-11-03 00:01:44 +0000709 */
710 li r0,__got2_entries@sectoff@l
711 la r3,GOT(_GOT2_TABLE_)
712 lwz r11,GOT(_GOT2_TABLE_)
713 mtctr r0
714 sub r11,r3,r11
715 addi r3,r3,-4
7161: lwzu r0,4(r3)
717 add r0,r0,r11
718 stw r0,0(r3)
719 bdnz 1b
720
721 /*
wdenk8bde7f72003-06-27 21:31:46 +0000722 * Now adjust the fixups and the pointers to the fixups
wdenk47d1a6e2002-11-03 00:01:44 +0000723 * in case we need to move ourselves again.
724 */
7252: li r0,__fixup_entries@sectoff@l
726 lwz r3,GOT(_FIXUP_TABLE_)
727 cmpwi r0,0
728 mtctr r0
729 addi r3,r3,-4
730 beq 4f
7313: lwzu r4,4(r3)
732 lwzux r0,r4,r11
733 add r0,r0,r11
734 stw r10,0(r3)
735 stw r0,0(r4)
736 bdnz 3b
7374:
738/* clear_bss: */
739 /*
740 * Now clear BSS segment
741 */
wdenk5d232d02003-05-22 22:52:13 +0000742 lwz r3,GOT(__bss_start)
wdenk47d1a6e2002-11-03 00:01:44 +0000743 lwz r4,GOT(_end)
744
745 cmplw 0, r3, r4
746 beq 6f
747
748 li r0, 0
7495:
750 stw r0, 0(r3)
751 addi r3, r3, 4
752 cmplw 0, r3, r4
753 bne 5b
7546:
755 mr r3, r10 /* Destination Address */
wdenk3a473b22004-01-03 00:43:19 +0000756#if defined(CONFIG_AMIGAONEG3SE) || \
757 defined(CONFIG_DB64360) || \
stroese0912e482004-12-16 18:10:54 +0000758 defined(CONFIG_DB64460) || \
759 defined(CONFIG_CPCI750)
wdenk7c7a23b2002-12-07 00:20:59 +0000760 mr r4, r9 /* Use RAM copy of the global data */
761#endif
wdenk47d1a6e2002-11-03 00:01:44 +0000762 bl after_reloc
763
764 /* not reached - end relocate_code */
765/*-----------------------------------------------------------------------*/
766
wdenk47d1a6e2002-11-03 00:01:44 +0000767 /*
768 * Copy exception vector code to low memory
769 *
770 * r3: dest_addr
771 * r7: source address, r8: end address, r9: target address
772 */
773 .globl trap_init
774trap_init:
775 lwz r7, GOT(_start)
776 lwz r8, GOT(_end_of_vectors)
777
wdenk682011f2003-06-03 23:54:09 +0000778 li r9, 0x100 /* reset vector always at 0x100 */
wdenk47d1a6e2002-11-03 00:01:44 +0000779
780 cmplw 0, r7, r8
781 bgelr /* return if r7>=r8 - just in case */
782
783 mflr r4 /* save link register */
7841:
785 lwz r0, 0(r7)
786 stw r0, 0(r9)
787 addi r7, r7, 4
788 addi r9, r9, 4
789 cmplw 0, r7, r8
790 bne 1b
791
792 /*
793 * relocate `hdlr' and `int_return' entries
794 */
795 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
796 li r8, Alignment - _start + EXC_OFF_SYS_RESET
7972:
798 bl trap_reloc
799 addi r7, r7, 0x100 /* next exception vector */
800 cmplw 0, r7, r8
801 blt 2b
802
803 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
804 bl trap_reloc
805
806 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
807 bl trap_reloc
808
809 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
810 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
8113:
812 bl trap_reloc
813 addi r7, r7, 0x100 /* next exception vector */
814 cmplw 0, r7, r8
815 blt 3b
816
817 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
818 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
8194:
820 bl trap_reloc
821 addi r7, r7, 0x100 /* next exception vector */
822 cmplw 0, r7, r8
823 blt 4b
824
825 /* enable execptions from RAM vectors */
826 mfmsr r7
827 li r8,MSR_IP
828 andc r7,r7,r8
829 mtmsr r7
830
831 mtlr r4 /* restore link register */
832 blr
833
834 /*
835 * Function: relocate entries for one exception vector
836 */
837trap_reloc:
838 lwz r0, 0(r7) /* hdlr ... */
839 add r0, r0, r3 /* ... += dest_addr */
840 stw r0, 0(r7)
841
842 lwz r0, 4(r7) /* int_return ... */
843 add r0, r0, r3 /* ... += dest_addr */
844 stw r0, 4(r7)
845
846 sync
847 isync
848
849 blr
850
851#ifdef CFG_INIT_RAM_LOCK
852lock_ram_in_cache:
853 /* Allocate Initial RAM in data cache.
854 */
855 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
856 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
857 li r2, ((CFG_INIT_RAM_END & ~31) + \
858 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
859 mtctr r2
8601:
861 dcbz r0, r3
862 addi r3, r3, 32
863 bdnz 1b
864
865 /* Lock the data cache */
866 mfspr r0, HID0
867 ori r0, r0, 0x1000
868 sync
869 mtspr HID0, r0
870 sync
871 blr
872
873.globl unlock_ram_in_cache
874unlock_ram_in_cache:
875 /* invalidate the INIT_RAM section */
876 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
877 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
878 li r2, ((CFG_INIT_RAM_END & ~31) + \
879 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
880 mtctr r2
8811: icbi r0, r3
882 addi r3, r3, 32
883 bdnz 1b
884 sync /* Wait for all icbi to complete on bus */
885 isync
886
887 /* Unlock the data cache and invalidate it */
888 mfspr r0, HID0
889 li r3,0x1000
890 andc r0,r0,r3
891 li r3,0x0400
892 or r0,r0,r3
893 sync
894 mtspr HID0, r0
895 sync
896 blr
897#endif