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Tim Schendekehl14c32612011-11-01 23:55:01 +00001/*
2 * (C) Copyright 2011
3 * egnite GmbH <info@egnite.de>
4 *
5 * Configuation settings for Ethernut 5 with AT91SAM9XE.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Tim Schendekehl14c32612011-11-01 23:55:01 +00008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include <asm/hardware.h>
14
15/* The first stage boot loader expects u-boot running at this address. */
16#define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */
17
18/* The first stage boot loader takes care of low level initialization. */
19#define CONFIG_SKIP_LOWLEVEL_INIT
20
21/* Set our official architecture number. */
22#define MACH_TYPE_ETHERNUT5 1971
23#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
24
25/* CPU information */
Tim Schendekehl14c32612011-11-01 23:55:01 +000026#define CONFIG_DISPLAY_CPUINFO /* Display at console. */
27#define CONFIG_ARCH_CPU_INIT
28
29/* ARM asynchronous clock */
30#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
31#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Tim Schendekehl14c32612011-11-01 23:55:01 +000032
33/* 32kB internal SRAM */
34#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
35#define CONFIG_SRAM_SIZE (32 << 10)
Rob Herring3d6ba912012-07-13 09:44:01 +000036#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
37 GENERATED_GBL_DATA_SIZE)
Tim Schendekehl14c32612011-11-01 23:55:01 +000038
39/* 128MB SDRAM in 1 bank */
40#define CONFIG_NR_DRAM_BANKS 1
41#define CONFIG_SYS_SDRAM_BASE 0x20000000
42#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
43#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
44#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
45#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
46#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
47#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
48 - CONFIG_SYS_MALLOC_LEN)
49
50/* 512kB on-chip NOR flash */
51# define CONFIG_SYS_MAX_FLASH_BANKS 1
52# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
53# define CONFIG_AT91_EFLASH
54# define CONFIG_SYS_MAX_FLASH_SECT 32
55# define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */
56# define CONFIG_EFLASH_PROTSECTORS 1
57
58/* 512kB DataFlash at NPCS0 */
59#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
60#define CONFIG_HAS_DATAFLASH
Tim Schendekehl14c32612011-11-01 23:55:01 +000061#define CONFIG_ATMEL_DATAFLASH_SPI
62#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
63#define DATAFLASH_TCSS (0x1a << 16)
64#define DATAFLASH_TCHS (0x1 << 24)
65
66#define CONFIG_ENV_IS_IN_SPI_FLASH
67#define CONFIG_ENV_OFFSET 0x3DE000
68#define CONFIG_ENV_SECT_SIZE (132 << 10)
69#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
70#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
71 + CONFIG_ENV_OFFSET)
72#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
73 + 0x042000)
74
75/* SPI */
76#define CONFIG_ATMEL_SPI
Tim Schendekehl14c32612011-11-01 23:55:01 +000077#define AT91_SPI_CLK 15000000
78
79/* Serial port */
80#define CONFIG_ATMEL_USART
81#define CONFIG_USART3 /* USART 3 is DBGU */
82#define CONFIG_BAUDRATE 115200
Tim Schendekehl14c32612011-11-01 23:55:01 +000083#define CONFIG_USART_BASE ATMEL_BASE_DBGU
84#define CONFIG_USART_ID ATMEL_ID_SYS
85
86/* Misc. hardware drivers */
87#define CONFIG_AT91_GPIO
88
89/* Command line configuration */
Tim Schendekehl14c32612011-11-01 23:55:01 +000090#define CONFIG_CMD_JFFS2
Tim Schendekehl14c32612011-11-01 23:55:01 +000091#define CONFIG_CMD_MTDPARTS
92#define CONFIG_CMD_NAND
Tim Schendekehl14c32612011-11-01 23:55:01 +000093
Joe Hershbergeref0f2f52015-06-22 16:15:30 -050094#ifndef MINIMAL_LOADER
Tim Schendekehl14c32612011-11-01 23:55:01 +000095#define CONFIG_CMD_BSP
Tim Schendekehl14c32612011-11-01 23:55:01 +000096#define CONFIG_CMD_DATE
Tim Schendekehl14c32612011-11-01 23:55:01 +000097#define CONFIG_CMD_REISER
98#define CONFIG_CMD_SAVES
Tim Schendekehl14c32612011-11-01 23:55:01 +000099#define CONFIG_CMD_UBI
100#define CONFIG_CMD_UBIFS
101#define CONFIG_CMD_UNZIP
Tim Schendekehl14c32612011-11-01 23:55:01 +0000102#endif
103
104/* NAND flash */
105#ifdef CONFIG_CMD_NAND
106#define CONFIG_SYS_MAX_NAND_DEVICE 1
107#define CONFIG_SYS_NAND_BASE 0x40000000
108#define CONFIG_SYS_NAND_DBW_8
109#define CONFIG_NAND_ATMEL
110/* our ALE is AD21 */
111#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
112/* our CLE is AD22 */
113#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmannac45bb12013-11-29 12:13:45 +0100114#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
Tim Schendekehl14c32612011-11-01 23:55:01 +0000115#endif
116
117/* JFFS2 */
118#ifdef CONFIG_CMD_JFFS2
Tim Schendekehl14c32612011-11-01 23:55:01 +0000119#define CONFIG_JFFS2_CMDLINE
120#define CONFIG_JFFS2_NAND
121#endif
122
123/* Ethernet */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000124#define CONFIG_NET_RETRY_COUNT 20
125#define CONFIG_MACB
126#define CONFIG_RMII
127#define CONFIG_PHY_ID 0
128#define CONFIG_MACB_SEARCH_PHY
129
130/* MMC */
131#ifdef CONFIG_CMD_MMC
132#define CONFIG_MMC
133#define CONFIG_GENERIC_MMC
134#define CONFIG_GENERIC_ATMEL_MCI
135#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
136#endif
137
138/* USB */
139#ifdef CONFIG_CMD_USB
140#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800141#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Tim Schendekehl14c32612011-11-01 23:55:01 +0000142#define CONFIG_USB_OHCI_NEW
143#define CONFIG_SYS_USB_OHCI_CPU_INIT
144#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
145#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
146#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Tim Schendekehl14c32612011-11-01 23:55:01 +0000147#endif
148
149/* RTC */
150#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
151#define CONFIG_RTC_PCF8563
152#define CONFIG_SYS_I2C_RTC_ADDR 0x51
153#endif
154
155/* I2C */
156#define CONFIG_SYS_MAX_I2C_BUS 1
Tim Schendekehl14c32612011-11-01 23:55:01 +0000157
Heiko Schocherea818db2013-01-29 08:53:15 +0100158#define CONFIG_SYS_I2C
159#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
160#define CONFIG_SYS_I2C_SOFT_SPEED 100000
161#define CONFIG_SYS_I2C_SOFT_SLAVE 0
162
Tim Schendekehl14c32612011-11-01 23:55:01 +0000163#define I2C_SOFT_DECLARATIONS
164
165#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
166#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
167
168#define I2C_INIT { \
169 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
170 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
171 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
172 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
173 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
174}
175
176#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
177#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
178#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
179#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
180#define I2C_DELAY udelay(100)
181#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
182
183/* DHCP/BOOTP options */
184#ifdef CONFIG_CMD_DHCP
185#define CONFIG_BOOTP_BOOTFILESIZE
186#define CONFIG_BOOTP_BOOTPATH
187#define CONFIG_BOOTP_GATEWAY
188#define CONFIG_BOOTP_HOSTNAME
189#define CONFIG_SYS_AUTOLOAD "n"
190#endif
191
192/* File systems */
193#define CONFIG_MTD_DEVICE
194#define CONFIG_MTD_PARTITIONS
195#if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
196#define MTDIDS_DEFAULT "nand0=atmel_nand"
197#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)"
198#endif
199#if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \
200 defined(CONFIG_CMD_USB) || defined(CONFIG_MMC)
201#define CONFIG_DOS_PARTITION
202#endif
203#define CONFIG_LZO
204#define CONFIG_RBTREE
205
206/* Boot command */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000207#define CONFIG_CMDLINE_TAG
208#define CONFIG_SETUP_MEMORY_TAGS
209#define CONFIG_INITRD_TAG
210#define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm"
211#if defined(CONFIG_CMD_NAND)
212#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
213 "root=/dev/mtdblock0 " \
214 MTDPARTS_DEFAULT \
215 " rw rootfstype=jffs2"
216#endif
217
218/* Misc. u-boot settings */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000219#define CONFIG_SYS_CBSIZE 256
220#define CONFIG_SYS_MAXARGS 16
221#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \
222 + sizeof(CONFIG_SYS_PROMPT))
223#define CONFIG_SYS_LONGHELP
224#define CONFIG_CMDLINE_EDITING
225
226#endif