blob: c1abcb63b020e8cc708b0b645df181ff2ff7b9ac [file] [log] [blame]
Andy Fleming87e29872015-11-04 15:48:32 -06001/*
2 * Based on corenet_ds.h
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10#define CONFIG_DISPLAY_BOARDINFO
11
12#define CONFIG_CYRUS
13
Andy Fleming87e29872015-11-04 15:48:32 -060014#if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040)
15#error Must call Cyrus CONFIG with a specific CPU enabled.
16#endif
17
Andy Fleming87e29872015-11-04 15:48:32 -060018#define CONFIG_MMC
19#define CONFIG_SDCARD
20#define CONFIG_FSL_SATA_V2
21#define CONFIG_PCIE3
22#define CONFIG_PCIE4
23#ifdef CONFIG_PPC_P5020
24#define CONFIG_SYS_FSL_RAID_ENGINE
25#define CONFIG_SYS_DPAA_RMAN
26#endif
27#define CONFIG_SYS_DPAA_PME
28
29/*
30 * Corenet DS style board configuration file
31 */
32#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
33#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
34#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
35#if defined(CONFIG_PPC_P5020)
36#define CONFIG_SYS_CLK_FREQ 133000000
37#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
38#elif defined(CONFIG_PPC_P5040)
39#define CONFIG_SYS_CLK_FREQ 100000000
40#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
41#endif
42
Andy Fleming87e29872015-11-04 15:48:32 -060043/* High Level Configuration Options */
44#define CONFIG_BOOKE
45#define CONFIG_E500 /* BOOKE e500 family */
46#define CONFIG_E500MC /* BOOKE e500mc family */
47#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
48#define CONFIG_MP /* support multiple processors */
49
Andy Fleming87e29872015-11-04 15:48:32 -060050#define CONFIG_SYS_MMC_MAX_DEVICE 1
51
52#ifndef CONFIG_SYS_TEXT_BASE
53#define CONFIG_SYS_TEXT_BASE 0xeff40000
54#endif
55
56#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
57#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
58#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
59#define CONFIG_PCI /* Enable PCI/PCIE */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040060#define CONFIG_PCIE1 /* PCIE controller 1 */
61#define CONFIG_PCIE2 /* PCIE controller 2 */
Andy Fleming87e29872015-11-04 15:48:32 -060062#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
63#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
64
65#define CONFIG_FSL_LAW /* Use common FSL init code */
66
67#define CONFIG_ENV_OVERWRITE
68
69#define CONFIG_SYS_NO_FLASH
70
71#if defined(CONFIG_SDCARD)
72#define CONFIG_SYS_EXTRA_ENV_RELOC
73#define CONFIG_ENV_IS_IN_MMC
74#define CONFIG_FSL_FIXED_MMC_LOCATION
75#define CONFIG_SYS_MMC_ENV_DEV 0
76#define CONFIG_ENV_SIZE 0x2000
77#define CONFIG_ENV_OFFSET (512 * 1658)
78#endif
79
80/*
81 * These can be toggled for performance analysis, otherwise use default.
82 */
83#define CONFIG_SYS_CACHE_STASHING
84#define CONFIG_BACKSIDE_L2_CACHE
85#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
86#define CONFIG_BTB /* toggle branch predition */
87#define CONFIG_DDR_ECC
88#ifdef CONFIG_DDR_ECC
89#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
90#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
91#endif
92
93#define CONFIG_ENABLE_36BIT_PHYS
94
95#ifdef CONFIG_PHYS_64BIT
96#define CONFIG_ADDR_MAP
97#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
98#endif
99
100/* test POST memory test */
101#undef CONFIG_POST
102#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
103#define CONFIG_SYS_MEMTEST_END 0x00400000
104#define CONFIG_SYS_ALT_MEMTEST
105#define CONFIG_PANIC_HANG /* do not reset board on panic */
106
107/*
108 * Config the L3 Cache as L3 SRAM
109 */
110#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
111#ifdef CONFIG_PHYS_64BIT
112#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
113#else
114#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
115#endif
116#define CONFIG_SYS_L3_SIZE (1024 << 10)
117#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
118
119#ifdef CONFIG_PHYS_64BIT
120#define CONFIG_SYS_DCSRBAR 0xf0000000
121#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
122#endif
123
124/*
125 * DDR Setup
126 */
127#define CONFIG_VERY_BIG_RAM
128#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
129#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
130
131#define CONFIG_DIMM_SLOTS_PER_CTLR 1
132#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
133
134#define CONFIG_DDR_SPD
135#define CONFIG_SYS_FSL_DDR3
136
137#define CONFIG_SYS_SPD_BUS_NUM 1
138#define SPD_EEPROM_ADDRESS1 0x51
139#define SPD_EEPROM_ADDRESS2 0x52
140#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
141
142/*
143 * Local Bus Definitions
144 */
145
146#define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */
147#ifdef CONFIG_PHYS_64BIT
148#define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
149#else
150#define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE
151#endif
152
153#define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */
154#ifdef CONFIG_PHYS_64BIT
155#define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
156#else
157#define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE
158#endif
159
160/* Set the local bus clock 1/16 of platform clock */
161#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1)
162
163#define CONFIG_SYS_BR0_PRELIM \
164(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
165#define CONFIG_SYS_BR1_PRELIM \
166(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
167
168#define CONFIG_SYS_OR0_PRELIM 0xfff00010
169#define CONFIG_SYS_OR1_PRELIM 0xfff00010
170
Andy Fleming87e29872015-11-04 15:48:32 -0600171#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
172
173#if defined(CONFIG_RAMBOOT_PBL)
174#define CONFIG_SYS_RAMBOOT
175#endif
176
177#define CONFIG_BOARD_EARLY_INIT_F
178#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
179#define CONFIG_MISC_INIT_R
180
181#define CONFIG_HWCONFIG
182
183/* define to use L1 as initial stack */
184#define CONFIG_L1_INIT_RAM
185#define CONFIG_SYS_INIT_RAM_LOCK
186#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
187#ifdef CONFIG_PHYS_64BIT
188#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
189#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
190/* The assembler doesn't like typecast */
191#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
192 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
193 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
194#else
195#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
196#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
197#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
198#endif
199#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
200
201#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
202#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
203
204#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
205#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
206
207/* Serial Port - controlled on board with jumper J8
208 * open - index 2
209 * shorted - index 1
210 */
211#define CONFIG_CONS_INDEX 1
Andy Fleming87e29872015-11-04 15:48:32 -0600212#define CONFIG_SYS_NS16550_SERIAL
213#define CONFIG_SYS_NS16550_REG_SIZE 1
214#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
215
216#define CONFIG_SYS_BAUDRATE_TABLE \
217{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
218
219#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
220#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
221#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
222#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
223
Andy Fleming87e29872015-11-04 15:48:32 -0600224/* I2C */
225#define CONFIG_SYS_I2C
226#define CONFIG_SYS_I2C_FSL
227#define CONFIG_I2C_MULTI_BUS
228#define CONFIG_I2C_CMD_TREE
229#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */
230#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
231#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
232#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */
233#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
234#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
235#define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */
236#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
237#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
238#define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */
239#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
240#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
241
242#define CONFIG_ID_EEPROM
243#define CONFIG_SYS_I2C_EEPROM_NXID
244#define CONFIG_SYS_EEPROM_BUS_NUM 0
245#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
246#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
247
248#define CONFIG_SYS_I2C_GENERIC_MAC
249#define CONFIG_SYS_I2C_MAC1_BUS 3
250#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
251#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
252#define CONFIG_SYS_I2C_MAC2_BUS 0
253#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
254#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
255
256#define CONFIG_CMD_DATE 1
257#define CONFIG_RTC_MCP79411 1
258#define CONFIG_SYS_RTC_BUS_NUM 3
259#define CONFIG_SYS_I2C_RTC_ADDR 0x6f
260
261/*
262 * eSPI - Enhanced SPI
263 */
Andy Fleming87e29872015-11-04 15:48:32 -0600264
265/*
266 * General PCI
267 * Memory space is mapped 1-1, but I/O space must start from 0.
268 */
269
270/* controller 1, direct to uli, tgtid 3, Base address 20000 */
271#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
272#ifdef CONFIG_PHYS_64BIT
273#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
274#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
275#else
276#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
277#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
278#endif
279#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
280#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
281#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
282#ifdef CONFIG_PHYS_64BIT
283#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
284#else
285#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
286#endif
287#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
288
289/* controller 2, Slot 2, tgtid 2, Base address 201000 */
290#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
291#ifdef CONFIG_PHYS_64BIT
292#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
293#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
294#else
295#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
296#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
297#endif
298#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
299#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
300#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
301#ifdef CONFIG_PHYS_64BIT
302#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
303#else
304#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
305#endif
306#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
307
308/* controller 3, Slot 1, tgtid 1, Base address 202000 */
309#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
310#ifdef CONFIG_PHYS_64BIT
311#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
312#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
313#else
314#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
315#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
316#endif
317#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
318#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
319#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
320#ifdef CONFIG_PHYS_64BIT
321#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
322#else
323#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
324#endif
325#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
326
327/* controller 4, Base address 203000 */
328#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
329#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
330#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
331#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
332#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
333#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
334
335/* Qman/Bman */
336#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
337#define CONFIG_SYS_BMAN_NUM_PORTALS 10
338#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
339#ifdef CONFIG_PHYS_64BIT
340#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
341#else
342#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
343#endif
344#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
345#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
346#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
347#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
348#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
349#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
350 CONFIG_SYS_BMAN_CENA_SIZE)
351#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
352#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
353#define CONFIG_SYS_QMAN_NUM_PORTALS 10
354#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
355#ifdef CONFIG_PHYS_64BIT
356#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
357#else
358#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
359#endif
360#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
361#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
362#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
363#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
364#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
365#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
366 CONFIG_SYS_QMAN_CENA_SIZE)
367#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
368#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
369
370#define CONFIG_SYS_DPAA_FMAN
371/* Default address of microcode for the Linux Fman driver */
372/*
373 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
374 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
375 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
376 */
377#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
378#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
379
380#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
381#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
382
383#ifdef CONFIG_SYS_DPAA_FMAN
384#define CONFIG_FMAN_ENET
385#define CONFIG_PHY_MICREL
386#define CONFIG_PHY_MICREL_KSZ9021
387#endif
388
389#ifdef CONFIG_PCI
390#define CONFIG_PCI_INDIRECT_BRIDGE
391#define CONFIG_PCI_PNP /* do pci plug-and-play */
392#define CONFIG_NET_MULTI
393
394#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
395#define CONFIG_DOS_PARTITION
396#endif /* CONFIG_PCI */
397
398/* SATA */
399#ifdef CONFIG_FSL_SATA_V2
400#define CONFIG_LIBATA
401#define CONFIG_FSL_SATA
402
403#define CONFIG_SYS_SATA_MAX_DEVICE 2
404#define CONFIG_SATA1
405#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
406#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
407#define CONFIG_SATA2
408#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
409#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
410
411#define CONFIG_LBA48
412#define CONFIG_CMD_SATA
413#define CONFIG_DOS_PARTITION
Andy Fleming87e29872015-11-04 15:48:32 -0600414#endif
415
416#ifdef CONFIG_FMAN_ENET
417#define CONFIG_SYS_TBIPA_VALUE 8
418#define CONFIG_MII /* MII PHY management */
419#define CONFIG_ETHPRIME "FM1@DTSEC4"
420#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
421#endif
422
423/*
424 * Environment
425 */
426#define CONFIG_LOADS_ECHO /* echo on for serial download */
427#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
428
429/*
430 * Command line configuration.
431 */
Andy Fleming87e29872015-11-04 15:48:32 -0600432#define CONFIG_CMD_ERRATA
Andy Fleming87e29872015-11-04 15:48:32 -0600433#define CONFIG_CMD_IRQ
Andy Fleming87e29872015-11-04 15:48:32 -0600434#define CONFIG_CMD_REGINFO
435
436#ifdef CONFIG_PCI
437#define CONFIG_CMD_PCI
438#endif
439
440/*
441 * USB
442 */
443#define CONFIG_HAS_FSL_DR_USB
444#define CONFIG_HAS_FSL_MPH_USB
445
446#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
Andy Fleming87e29872015-11-04 15:48:32 -0600447#define CONFIG_USB_EHCI
448#define CONFIG_USB_EHCI_FSL
449#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Andy Fleming87e29872015-11-04 15:48:32 -0600450#define CONFIG_EHCI_IS_TDI
451#define CONFIG_USB_KEYBOARD
Andy Fleming9d243b12016-01-06 15:34:50 -0600452#define CONFIG_SYS_STDIO_DEREGISTER
Andy Fleming87e29872015-11-04 15:48:32 -0600453#define CONFIG_SYS_USB_EVENT_POLL
454 /* _VIA_CONTROL_EP */
455#define CONFIG_CONSOLE_MUX
456#define CONFIG_SYS_CONSOLE_IS_IN_ENV
457#endif
458
459#ifdef CONFIG_MMC
460#define CONFIG_FSL_ESDHC
461#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
462#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
Andy Fleming87e29872015-11-04 15:48:32 -0600463#define CONFIG_GENERIC_MMC
Andy Fleming87e29872015-11-04 15:48:32 -0600464#define CONFIG_DOS_PARTITION
465#endif
466
467/*
468 * Miscellaneous configurable options
469 */
470#define CONFIG_SYS_LONGHELP /* undef to save memory */
471#define CONFIG_CMDLINE_EDITING /* Command-line editing */
472#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
473#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Andy Fleming87e29872015-11-04 15:48:32 -0600474#ifdef CONFIG_CMD_KGDB
475#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
476#else
477#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
478#endif
479#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
480#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
481#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
482
483/*
484 * For booting Linux, the board info and command line data
485 * have to be in the first 64 MB of memory, since this is
486 * the maximum mapped by the Linux kernel during initialization.
487 */
488#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
489#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
490
491#ifdef CONFIG_CMD_KGDB
492#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
493#endif
494
495/*
496 * Environment Configuration
497 */
498#define CONFIG_ROOTPATH "/opt/nfsroot"
499#define CONFIG_BOOTFILE "uImage"
500#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
501
502/* default location for tftp and bootm */
503#define CONFIG_LOADADDR 1000000
504
Andy Fleming87e29872015-11-04 15:48:32 -0600505
506#define CONFIG_BAUDRATE 115200
507
508#define __USB_PHY_TYPE utmi
509
510#define CONFIG_EXTRA_ENV_SETTINGS \
511"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
512"bank_intlv=cs0_cs1;" \
513"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
514"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
515"netdev=eth0\0" \
516"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
517"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
518"consoledev=ttyS0\0" \
519"ramdiskaddr=2000000\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500520"fdtaddr=1e00000\0" \
Andy Fleming87e29872015-11-04 15:48:32 -0600521"bdev=sda3\0"
522
523#define CONFIG_HDBOOT \
524"setenv bootargs root=/dev/$bdev rw " \
525"console=$consoledev,$baudrate $othbootargs;" \
526"tftp $loadaddr $bootfile;" \
527"tftp $fdtaddr $fdtfile;" \
528"bootm $loadaddr - $fdtaddr"
529
530#define CONFIG_NFSBOOTCOMMAND \
531"setenv bootargs root=/dev/nfs rw " \
532"nfsroot=$serverip:$rootpath " \
533"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
534"console=$consoledev,$baudrate $othbootargs;" \
535"tftp $loadaddr $bootfile;" \
536"tftp $fdtaddr $fdtfile;" \
537"bootm $loadaddr - $fdtaddr"
538
539#define CONFIG_RAMBOOTCOMMAND \
540"setenv bootargs root=/dev/ram rw " \
541"console=$consoledev,$baudrate $othbootargs;" \
542"tftp $ramdiskaddr $ramdiskfile;" \
543"tftp $loadaddr $bootfile;" \
544"tftp $fdtaddr $fdtfile;" \
545"bootm $loadaddr $ramdiskaddr $fdtaddr"
546
547#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
548
549#include <asm/fsl_secure_boot.h>
550
551#ifdef CONFIG_SECURE_BOOT
552#endif
553
554#endif /* __CONFIG_H */