| Rajeshwari Shinde | 02cfce3 | 2012-10-25 19:49:25 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Samsung Electronics |
| 3 | * R. Chandrasekar <rcsekar@samsung.com> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #ifndef __I2S_REGS_H__ |
| 25 | #define __I2S_REGS_H__ |
| 26 | |
| 27 | #define CON_TXFIFO_FULL (1 << 8) |
| 28 | #define CON_TXCH_PAUSE (1 << 4) |
| 29 | #define CON_ACTIVE (1 << 0) |
| 30 | |
| 31 | #define MOD_BLCP_SHIFT 24 |
| 32 | #define MOD_BLCP_16BIT (0 << MOD_BLCP_SHIFT) |
| 33 | #define MOD_BLCP_8BIT (1 << MOD_BLCP_SHIFT) |
| 34 | #define MOD_BLCP_24BIT (2 << MOD_BLCP_SHIFT) |
| 35 | #define MOD_BLCP_MASK (3 << MOD_BLCP_SHIFT) |
| 36 | |
| 37 | #define MOD_BLC_16BIT (0 << 13) |
| 38 | #define MOD_BLC_8BIT (1 << 13) |
| 39 | #define MOD_BLC_24BIT (2 << 13) |
| 40 | #define MOD_BLC_MASK (3 << 13) |
| 41 | |
| 42 | #define MOD_SLAVE (1 << 11) |
| 43 | #define MOD_MASK (3 << 8) |
| 44 | #define MOD_LR_LLOW (0 << 7) |
| 45 | #define MOD_LR_RLOW (1 << 7) |
| 46 | #define MOD_SDF_IIS (0 << 5) |
| 47 | #define MOD_SDF_MSB (1 << 5) |
| 48 | #define MOD_SDF_LSB (2 << 5) |
| 49 | #define MOD_SDF_MASK (3 << 5) |
| 50 | #define MOD_RCLK_256FS (0 << 3) |
| 51 | #define MOD_RCLK_512FS (1 << 3) |
| 52 | #define MOD_RCLK_384FS (2 << 3) |
| 53 | #define MOD_RCLK_768FS (3 << 3) |
| 54 | #define MOD_RCLK_MASK (3 << 3) |
| 55 | #define MOD_BCLK_32FS (0 << 1) |
| 56 | #define MOD_BCLK_48FS (1 << 1) |
| 57 | #define MOD_BCLK_16FS (2 << 1) |
| 58 | #define MOD_BCLK_24FS (3 << 1) |
| 59 | #define MOD_BCLK_MASK (3 << 1) |
| 60 | |
| 61 | #define MOD_CDCLKCON (1 << 12) |
| 62 | |
| 63 | #define FIC_TXFLUSH (1 << 15) |
| 64 | #define FIC_RXFLUSH (1 << 7) |
| 65 | |
| 66 | #endif /* __I2S_REGS_H__ */ |