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Wolfgang Denkba94a1b2006-05-30 15:56:48 +02001/*
Stefan Roese1bbf5ea2007-01-30 15:01:49 +01002 * (C) Copyright 2006-2007
Wolfgang Denkba94a1b2006-05-30 15:56:48 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Configuation settings for the PDNB3 board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 * (easy to change)
32 */
33#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
34#define CONFIG_PDNB3 1 /* on an PDNB3 board */
35
Marek Vasut8e807ec2012-03-06 00:45:35 +010036#define CONFIG_MACH_TYPE 1002
37
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020038#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
39#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
40
41/*
42 * Ethernet
43 */
44#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020045#define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */
46#define CONFIG_HAS_ETH1
47#define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */
48#define CONFIG_MII 1 /* MII PHY management */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020050
51/*
52 * Misc configuration options
53 */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020054#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020056
57#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
58#define CONFIG_SETUP_MEMORY_TAGS 1
59#define CONFIG_INITRD_TAG 1
60
61/*
62 * Size of malloc() pool
63 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_MALLOC_LEN (1 << 20)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020065
66/* allow to overwrite serial and ethaddr */
67#define CONFIG_ENV_OVERWRITE
68
Jean-Christophe PLAGNIOL-VILLARD930590f2009-01-31 09:10:48 +010069#define CONFIG_IXP_SERIAL
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020070#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020072
Jon Loeliger26a34562007-07-04 22:33:17 -050073
74/*
Jon Loeliger079a1362007-07-10 10:12:10 -050075 * BOOTP options
76 */
77#define CONFIG_BOOTP_BOOTFILESIZE
78#define CONFIG_BOOTP_BOOTPATH
79#define CONFIG_BOOTP_GATEWAY
80#define CONFIG_BOOTP_HOSTNAME
81
82
83/*
Jon Loeliger26a34562007-07-04 22:33:17 -050084 * Command line configuration.
85 */
86#include <config_cmd_default.h>
87
88#define CONFIG_CMD_DHCP
89#define CONFIG_CMD_DATE
90#define CONFIG_CMD_NET
91#define CONFIG_CMD_MII
92#define CONFIG_CMD_I2C
93#define CONFIG_CMD_ELF
94#define CONFIG_CMD_PING
95
96#if !defined(CONFIG_SCPU)
97#define CONFIG_CMD_NAND
Stefan Roese9d8d5a52007-01-18 16:05:47 +010098#endif
99
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200100
101#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
102#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
103
104/*
105 * Miscellaneous configurable options
106 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_LONGHELP /* undef to save memory */
108#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
109#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
110#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
111#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
112#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
115#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
116#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200117
Michael Schwingen904ec572011-05-23 00:00:11 +0200118#define CONFIG_IXP425_TIMER_CLK 66666666
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200120 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200122
123/*
124 * Stack sizes
125 *
126 * The stack sizes are set up in start.S using the settings below
127 */
128#define CONFIG_STACKSIZE (128*1024) /* regular stack */
129#ifdef CONFIG_USE_IRQ
130#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
131#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
132#endif
133
134/***************************************************************
135 * Platform/Board specific defines start here.
136 ***************************************************************/
137
138/*-----------------------------------------------------------------------
139 * Default configuration (environment varibles...)
140 *----------------------------------------------------------------------*/
141#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100142 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200143 "echo"
144
145#undef CONFIG_BOOTARGS
146
147#define CONFIG_EXTRA_ENV_SETTINGS \
148 "netdev=eth0\0" \
149 "hostname=pdnb3\0" \
150 "nfsargs=setenv bootargs root=/dev/nfs rw " \
151 "nfsroot=${serverip}:${rootpath}\0" \
152 "ramargs=setenv bootargs root=/dev/ram rw\0" \
153 "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
154 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
155 ":${hostname}:${netdev}:off panic=1\0" \
156 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \
157 "mtdparts=${mtdparts}\0" \
158 "flash_nfs=run nfsargs addip addtty;" \
159 "bootm ${kernel_addr}\0" \
160 "flash_self=run ramargs addip addtty;" \
161 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
162 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
163 "bootm\0" \
164 "rootpath=/opt/buildroot\0" \
165 "bootfile=/tftpboot/netbox/uImage\0" \
166 "kernel_addr=50080000\0" \
167 "ramdisk_addr=50200000\0" \
168 "load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \
169 "update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \
170 "cp.b 100000 50000000 ${filesize};" \
171 "setenv filesize;saveenv\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100172 "upd=run load update\0" \
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200173 "ipaddr=10.0.0.233\0" \
174 "serverip=10.0.0.152\0" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200175 "netmask=255.255.0.0\0" \
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200176 "ethaddr=c6:6f:13:36:f3:81\0" \
177 "eth1addr=c6:6f:13:36:f3:82\0" \
178 "mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \
179 "4k@508k(renv)\0" \
180 ""
181#define CONFIG_BOOTCOMMAND "run net_nfs"
182
183/*
184 * Physical Memory Map
185 */
186#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
187#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
188#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
189
Michael Schwingen904ec572011-05-23 00:00:11 +0200190#define CONFIG_SYS_TEXT_BASE 0x50000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_FLASH_BASE 0x50000000
192#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100193#if defined(CONFIG_SCPU)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100195#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100197#endif
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200198
199/*
200 * Expansion bus settings
201 */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100202#if defined(CONFIG_SCPU)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_EXP_CS0 0x94d23C42 /* 8bit, max size */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100204#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_EXP_CS0 0x94913C43 /* 8bit, max size */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100206#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_EXP_CS1 0x85000043 /* 8bit, 512bytes */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200208
209/*
210 * SDRAM settings
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_SDR_CONFIG 0x18
213#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
214#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200215
216/*
217 * FLASH and environment organization
218 */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100219#if defined(CONFIG_SCPU)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200221#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100223#endif
224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
228#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
231#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
234#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
235#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200236/*
237 * The following defines are added for buggy IOP480 byte interface.
238 * All other boards should use the standard values (CPCI405 etc.)
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
241#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
242#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200245
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200246#define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100249#if defined(CONFIG_SCPU)
Stefan Roese1bbf5ea2007-01-30 15:01:49 +0100250/* no redundant environment on SCPU */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200251#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
252#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100253#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200254#define CONFIG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
255#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200256
257/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200258#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
259#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese1bbf5ea2007-01-30 15:01:49 +0100260#endif
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200261
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100262#if !defined(CONFIG_SCPU)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200263/*
264 * NAND-FLASH stuff
265 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wolfgang Denk2eb99ca2009-07-18 21:52:24 +0200267#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100268#endif
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200269
270/*
271 * GPIO settings
272 */
273
274/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_GPIO_PRG 12 /* FPGA program pin (cpu output)*/
276#define CONFIG_SYS_GPIO_CLK 10 /* FPGA clk pin (cpu output) */
277#define CONFIG_SYS_GPIO_DATA 14 /* FPGA data pin (cpu output) */
278#define CONFIG_SYS_GPIO_INIT 13 /* FPGA init pin (cpu input) */
279#define CONFIG_SYS_GPIO_DONE 11 /* FPGA done pin (cpu input) */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200280
281/* other GPIO's */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_GPIO_RESTORE_INT 0
283#define CONFIG_SYS_GPIO_RESTART_INT 1
284#define CONFIG_SYS_GPIO_SYS_RUNNING 2
285#define CONFIG_SYS_GPIO_PCI_INTA 3
286#define CONFIG_SYS_GPIO_PCI_INTB 4
287#define CONFIG_SYS_GPIO_I2C_SCL 6
288#define CONFIG_SYS_GPIO_I2C_SDA 7
289#define CONFIG_SYS_GPIO_FPGA_RESET 9
290#define CONFIG_SYS_GPIO_CLK_33M 15
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200291
292/*
293 * I2C stuff
294 */
295
296/* enable I2C and select the hardware/software driver */
297#undef CONFIG_HARD_I2C /* I2C with hardware support */
298#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
299
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_I2C_SPEED 83000 /* 83 kHz is supposed to work */
301#define CONFIG_SYS_I2C_SLAVE 0xFE
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200302
303/*
304 * Software (bit-bang) I2C driver configuration
305 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define PB_SCL (1 << CONFIG_SYS_GPIO_I2C_SCL)
307#define PB_SDA (1 << CONFIG_SYS_GPIO_I2C_SDA)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200308
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define I2C_INIT GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL)
310#define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA)
311#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200312#define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); \
314 else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA)
315#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); \
316 else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200317#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
318
319/*
320 * I2C RTC
321 */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100322#if 0 /* test-only */
323#define CONFIG_RTC_DS1340 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100325#else
326/* M41T11 Serial Access Timekeeper(R) SRAM */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200327#define CONFIG_RTC_M41T11 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_I2C_RTC_ADDR 0x68
329#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
Stefan Roese9d8d5a52007-01-18 16:05:47 +0100330#endif
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200331
332/*
333 * Spartan3 FPGA configuration support
334 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200336
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_FPGA_PRG (1 << CONFIG_SYS_GPIO_PRG) /* FPGA program pin (cpu output)*/
338#define CONFIG_SYS_FPGA_CLK (1 << CONFIG_SYS_GPIO_CLK) /* FPGA clk pin (cpu output) */
339#define CONFIG_SYS_FPGA_DATA (1 << CONFIG_SYS_GPIO_DATA) /* FPGA data pin (cpu output) */
340#define CONFIG_SYS_FPGA_INIT (1 << CONFIG_SYS_GPIO_INIT) /* FPGA init pin (cpu input) */
341#define CONFIG_SYS_FPGA_DONE (1 << CONFIG_SYS_GPIO_DONE) /* FPGA done pin (cpu input) */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200342
343/*
344 * Cache Configuration
345 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_CACHELINE_SIZE 32
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200347
Michael Schwingen904ec572011-05-23 00:00:11 +0200348/* additions for new relocation code, must be added to all boards */
349#define CONFIG_SYS_SDRAM_BASE 0x00000000
350#define CONFIG_SYS_INIT_SP_ADDR \
351 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
352
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200353#endif /* __CONFIG_H */