Dirk Eibach | 89b8619 | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
| 4 | * |
| 5 | * Based on include/configs/yosemite.h |
| 6 | * (C) Copyright 2005-2007 |
| 7 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 8 | * |
Wolfgang Denk | 3765b3e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 9 | * SPDX-License-Identifier: GPL-2.0+ |
Dirk Eibach | 89b8619 | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | /* |
| 13 | * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module |
| 14 | */ |
| 15 | #ifndef __CONFIG_H |
| 16 | #define __CONFIG_H |
| 17 | |
| 18 | /* |
| 19 | * High Level Configuration Options |
| 20 | */ |
| 21 | #define CONFIG_440GR 1 /* Specific PPC440GR support */ |
| 22 | #define CONFIG_HOSTNAME gdppc440etx |
| 23 | #define CONFIG_440 1 /* ... PPC440 family */ |
Dirk Eibach | 89b8619 | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 24 | #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ |
| 25 | |
Wolfgang Denk | 2ae1824 | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 26 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
| 27 | |
Dirk Eibach | 89b8619 | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 28 | /* |
| 29 | * Include common defines/options for all AMCC eval boards |
| 30 | */ |
| 31 | #include "amcc-common.h" |
| 32 | |
| 33 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/ |
| 34 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
Dirk Eibach | d9f923f | 2014-07-25 10:10:24 +0200 | [diff] [blame] | 35 | #define CONFIG_SYS_GENERIC_BOARD |
Dirk Eibach | 89b8619 | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 36 | |
Dirk Eibach | 996d88d | 2012-04-26 03:54:25 +0000 | [diff] [blame] | 37 | #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ |
| 38 | #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ |
| 39 | #define CONFIG_AUTOBOOT_STOP_STR " " |
| 40 | |
Dirk Eibach | 89b8619 | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 41 | /* |
| 42 | * Base addresses -- Note these are effective addresses where the |
| 43 | * actual resources get mapped (not physical addresses) |
| 44 | */ |
| 45 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ |
| 46 | #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ |
| 47 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 |
| 48 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 |
| 49 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 |
| 50 | |
| 51 | /*Don't change either of these*/ |
Dirk Eibach | 89b8619 | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 52 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ |
| 53 | /*Don't change either of these*/ |
| 54 | |
| 55 | #define CONFIG_SYS_USB_DEVICE 0x50000000 |
| 56 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 |
| 57 | |
| 58 | /* |
| 59 | * Initial RAM & stack pointer (placed in SDRAM) |
| 60 | */ |
| 61 | #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/ |
| 62 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 63 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 64 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 65 | - GENERATED_GBL_DATA_SIZE) |
Dirk Eibach | 89b8619 | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 66 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 67 | |
| 68 | /* |
| 69 | * Serial Port |
| 70 | */ |
Stefan Roese | 550650d | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 71 | #define CONFIG_CONS_INDEX 2 /* Use UART1 */ |
| 72 | #define CONFIG_SYS_NS16550 |
| 73 | #define CONFIG_SYS_NS16550_SERIAL |
| 74 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 75 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
Dirk Eibach | 89b8619 | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 76 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ |
Dirk Eibach | 89b8619 | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 77 | |
| 78 | /* |
| 79 | * Environment |
| 80 | * Define here the location of the environment variables (FLASH or EEPROM). |
| 81 | * Note: DENX encourages to use redundant environment in FLASH. |
| 82 | */ |
| 83 | #define CONFIG_ENV_IS_IN_FLASH 1 /* FLASH for env. vars*/ |
| 84 | |
| 85 | /* |
| 86 | * FLASH related |
| 87 | */ |
| 88 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/ |
| 89 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
| 90 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/ |
| 91 | |
| 92 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 93 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */ |
| 94 | |
| 95 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms)*/ |
| 96 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms)*/ |
| 97 | |
| 98 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/ |
| 99 | |
| 100 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
| 101 | |
| 102 | #ifdef CONFIG_ENV_IS_IN_FLASH |
| 103 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ |
| 104 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
| 105 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */ |
| 106 | |
| 107 | /* Address and size of Redundant Environment Sector */ |
| 108 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
| 109 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
| 110 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
| 111 | |
| 112 | /* |
| 113 | * DDR SDRAM |
| 114 | */ |
| 115 | #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/ |
| 116 | #define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ |
| 117 | #define CONFIG_SYS_SDRAM_BANKS (2) |
| 118 | |
| 119 | #define CONFIG_SDRAM_BANK0 |
| 120 | #define CONFIG_SDRAM_BANK1 |
| 121 | |
| 122 | #define CONFIG_SYS_SDRAM0_TR0 0x410a4012 |
| 123 | #define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000 |
| 124 | #define CONFIG_SYS_SDRAM0_RTR 0x04080000 |
| 125 | #define CONFIG_SYS_SDRAM0_CFG0 0x80000000 |
| 126 | |
| 127 | #undef CONFIG_SDRAM_ECC |
| 128 | |
| 129 | /* |
| 130 | * I2C |
| 131 | */ |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame] | 132 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
Dirk Eibach | 89b8619 | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 133 | |
| 134 | /* |
| 135 | * Default environment variables |
| 136 | */ |
| 137 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 138 | CONFIG_AMCC_DEF_ENV \ |
| 139 | CONFIG_AMCC_DEF_ENV_POWERPC \ |
| 140 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ |
| 141 | "kernel_addr=fc000000\0" \ |
| 142 | "ramdisk_addr=fc180000\0" \ |
| 143 | "" |
| 144 | |
| 145 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
| 146 | #define CONFIG_PHY_ADDR 1 |
| 147 | #define CONFIG_PHY1_ADDR 3 |
| 148 | |
| 149 | #ifdef DEBUG |
| 150 | #define CONFIG_PANIC_HANG |
| 151 | #endif |
| 152 | |
| 153 | /* |
| 154 | * Commands additional to the ones defined in amcc-common.h |
| 155 | */ |
| 156 | #define CONFIG_CMD_PCI |
| 157 | #undef CONFIG_CMD_EEPROM |
| 158 | |
| 159 | /* |
| 160 | * PCI stuff |
| 161 | */ |
| 162 | |
| 163 | /* General PCI */ |
| 164 | #define CONFIG_PCI /* include pci support */ |
Gabor Juhos | 842033e | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 165 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
Dirk Eibach | 89b8619 | 2008-12-09 13:12:40 +0100 | [diff] [blame] | 166 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
| 167 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/ |
| 168 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \ |
| 169 | CONFIG_SYS_PCI_MEMBASE*/ |
| 170 | |
| 171 | /* Board-specific PCI */ |
| 172 | #define CONFIG_SYS_PCI_TARGET_INIT |
| 173 | #define CONFIG_SYS_PCI_MASTER_INIT |
| 174 | |
| 175 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
| 176 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */ |
| 177 | |
| 178 | /* |
| 179 | * External Bus Controller (EBC) Setup |
| 180 | */ |
| 181 | #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE |
| 182 | |
| 183 | /* Memory Bank 0 (NOR-FLASH) initialization */ |
| 184 | #define CONFIG_SYS_EBC_PB0AP 0x03017200 |
| 185 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) |
| 186 | |
| 187 | #endif /* __CONFIG_H */ |