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Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +09001/*
2 * include/configs/lager.h
3 * This file is lager board configuration.
4 *
Nobuhiro Iwamatsu5ca6dfe2014-11-10 14:34:07 +09005 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +09006 *
7 * SPDX-License-Identifier: GPL-2.0
8 */
9
10#ifndef __LAGER_H
11#define __LAGER_H
12
13#undef DEBUG
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090014#define CONFIG_R8A7790
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090015#define CONFIG_RMOBILE_BOARD_STRING "Lager"
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090016
Nobuhiro Iwamatsu5ca6dfe2014-11-10 14:34:07 +090017#include "rcar-gen2-common.h"
Nobuhiro Iwamatsud80149b2014-03-31 15:22:31 +090018
Nobuhiro Iwamatsufb6f6002014-10-31 16:16:26 +090019#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
20#define CONFIG_SYS_TEXT_BASE 0xB0000000
21#else
Nobuhiro Iwamatsu0e05b212014-01-08 10:32:22 +090022#define CONFIG_SYS_TEXT_BASE 0xE8080000
Nobuhiro Iwamatsufb6f6002014-10-31 16:16:26 +090023#endif
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090024
25/* STACK */
Nobuhiro Iwamatsufb6f6002014-10-31 16:16:26 +090026#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
27#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC
28#else
29#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC
30#endif
31#define STACK_AREA_SIZE 0xC000
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090032#define LOW_LEVEL_MERAM_STACK \
33 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
34
35/* MEMORY */
Nobuhiro Iwamatsu5ca6dfe2014-11-10 14:34:07 +090036#define RCAR_GEN2_SDRAM_BASE 0x40000000
37#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
38#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090039
40/* SCIF */
41#define CONFIG_SCIF_CONSOLE
42#define CONFIG_CONS_SCIF0
Nobuhiro Iwamatsuc252d642014-07-28 08:35:05 +090043#define CONFIG_SCIF_USE_EXT_CLK
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090044
Nobuhiro Iwamatsu5ca6dfe2014-11-10 14:34:07 +090045/* SPI */
Nobuhiro Iwamatsu0e05b212014-01-08 10:32:22 +090046#define CONFIG_SPI
47#define CONFIG_SPI_FLASH_BAR
48#define CONFIG_SH_QSPI
49#define CONFIG_SPI_FLASH
50#define CONFIG_SPI_FLASH_SPANSION
51#define CONFIG_SYS_NO_FLASH
52
Nobuhiro Iwamatsu23565c62013-10-20 20:28:24 +090053/* SH Ether */
54#define CONFIG_NET_MULTI
55#define CONFIG_SH_ETHER
56#define CONFIG_SH_ETHER_USE_PORT 0
57#define CONFIG_SH_ETHER_PHY_ADDR 0x1
58#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
59#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
60#define CONFIG_SH_ETHER_CACHE_WRITEBACK
61#define CONFIG_SH_ETHER_CACHE_INVALIDATE
62#define CONFIG_PHYLIB
63#define CONFIG_PHY_MICREL
64#define CONFIG_BITBANGMII
65#define CONFIG_BITBANGMII_MULTI
66
Nobuhiro Iwamatsub9107ad2013-09-30 10:08:40 +090067/* I2C */
68#define CONFIG_SYS_I2C
69#define CONFIG_SYS_I2C_RCAR
Nobuhiro Iwamatsub9107ad2013-09-30 10:08:40 +090070#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
Nobuhiro Iwamatsub9107ad2013-09-30 10:08:40 +090071#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
Nobuhiro Iwamatsub9107ad2013-09-30 10:08:40 +090072#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
Nobuhiro Iwamatsub9107ad2013-09-30 10:08:40 +090073#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
74#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
75
Nobuhiro Iwamatsub9986be2013-10-10 09:13:41 +090076#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
77
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090078/* Board Clock */
Nobuhiro Iwamatsub1f78a22014-03-31 14:03:07 +090079#define RMOBILE_XTAL_CLK 20000000u
80#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
81#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
82#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090083#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
84#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
Nobuhiro Iwamatsub9107ad2013-09-30 10:08:40 +090085#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
Nobuhiro Iwamatsuc33e4f12014-07-28 08:11:21 +090086#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090087
88#define CONFIG_SYS_TMU_CLK_DIV 4
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090089
Nobuhiro Iwamatsu5c4bb962014-03-27 14:14:58 +090090/* USB */
91#define CONFIG_USB_EHCI
92#define CONFIG_USB_EHCI_RMOBILE
Nobuhiro Iwamatsu5906fad2014-07-28 15:29:31 +090093#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
Nobuhiro Iwamatsu5c4bb962014-03-27 14:14:58 +090094#define CONFIG_USB_STORAGE
95
Nobuhiro Iwamatsu8e2e5882014-12-02 16:52:24 +090096/* Module stop status bits */
97/* INTC-RT */
98#define CONFIG_SMSTP0_ENA 0x00400000
99/* MSIF */
100#define CONFIG_SMSTP2_ENA 0x00002000
101/* INTC-SYS, IRQC */
102#define CONFIG_SMSTP4_ENA 0x00000180
103/* SCIF0 */
104#define CONFIG_SMSTP7_ENA 0x00200000
105
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +0900106#endif /* __LAGER_H */