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gerrit.cesnet.cz / github / trini / u-boot / 8db13d63157811c839d15a313d9f2d2f5fd10af3 / . / include / asm-blackfin / mem_init.h
blob: d9d8bf9ba2587740acd7699f05c04a2ce142bb19 [file] [log] [blame]
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100[diff] [blame]1/*
2 * U-boot - mem_init.h Header file for memory initialization
3 *
4 * Copyright (c) 2005 blackfin.uclinux.org
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800[diff] [blame]25#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \
26 CONFIG_MEM_MT48LC64M4A2FB_7E || \
27 CONFIG_MEM_MT48LC16M8A2TG_75 || \
28 CONFIG_MEM_MT48LC8M16A2TG_7E || \
Aubrey Li8db13d62007-03-10 23:49:29 +0800[diff] [blame^]29 CONFIG_MEM_MT48LC8M32B2B5_7 || \
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800[diff] [blame]30 CONFIG_MEM_MT48LC32M8A2_75)
31
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100[diff] [blame]32 #if ( CONFIG_SCLK_HZ > 119402985 )
33 #define SDRAM_tRP TRP_2
34 #define SDRAM_tRP_num 2
35 #define SDRAM_tRAS TRAS_7
36 #define SDRAM_tRAS_num 7
37 #define SDRAM_tRCD TRCD_2
38 #define SDRAM_tWR TWR_2
39 #endif
40 #if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 )
41 #define SDRAM_tRP TRP_2
42 #define SDRAM_tRP_num 2
43 #define SDRAM_tRAS TRAS_6
44 #define SDRAM_tRAS_num 6
45 #define SDRAM_tRCD TRCD_2
46 #define SDRAM_tWR TWR_2
47 #endif
48 #if ( CONFIG_SCLK_HZ > 89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 )
49 #define SDRAM_tRP TRP_2
50 #define SDRAM_tRP_num 2
51 #define SDRAM_tRAS TRAS_5
52 #define SDRAM_tRAS_num 5
53 #define SDRAM_tRCD TRCD_2
54 #define SDRAM_tWR TWR_2
55 #endif
56 #if ( CONFIG_SCLK_HZ > 74626866 ) && ( CONFIG_SCLK_HZ <= 89552239 )
57 #define SDRAM_tRP TRP_2
58 #define SDRAM_tRP_num 2
59 #define SDRAM_tRAS TRAS_4
60 #define SDRAM_tRAS_num 4
61 #define SDRAM_tRCD TRCD_2
62 #define SDRAM_tWR TWR_2
63 #endif
64 #if ( CONFIG_SCLK_HZ > 66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 )
65 #define SDRAM_tRP TRP_2
66 #define SDRAM_tRP_num 2
67 #define SDRAM_tRAS TRAS_3
68 #define SDRAM_tRAS_num 3
69 #define SDRAM_tRCD TRCD_2
70 #define SDRAM_tWR TWR_2
71 #endif
72 #if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
73 #define SDRAM_tRP TRP_1
74 #define SDRAM_tRP_num 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800[diff] [blame]75 #define SDRAM_tRAS TRAS_3
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100[diff] [blame]76 #define SDRAM_tRAS_num 3
77 #define SDRAM_tRCD TRCD_1
78 #define SDRAM_tWR TWR_2
79 #endif
80 #if ( CONFIG_SCLK_HZ > 44776119 ) && ( CONFIG_SCLK_HZ <= 59701493 )
81 #define SDRAM_tRP TRP_1
82 #define SDRAM_tRP_num 1
83 #define SDRAM_tRAS TRAS_3
84 #define SDRAM_tRAS_num 3
85 #define SDRAM_tRCD TRCD_1
86 #define SDRAM_tWR TWR_2
87 #endif
88 #if ( CONFIG_SCLK_HZ > 29850746 ) && ( CONFIG_SCLK_HZ <= 44776119 )
89 #define SDRAM_tRP TRP_1
90 #define SDRAM_tRP_num 1
91 #define SDRAM_tRAS TRAS_2
92 #define SDRAM_tRAS_num 2
93 #define SDRAM_tRCD TRCD_1
94 #define SDRAM_tWR TWR_2
95 #endif
96 #if ( CONFIG_SCLK_HZ <= 29850746 )
97 #define SDRAM_tRP TRP_1
98 #define SDRAM_tRP_num 1
99 #define SDRAM_tRAS TRAS_1
100 #define SDRAM_tRAS_num 1
101 #define SDRAM_tRCD TRCD_1
102 #define SDRAM_tWR TWR_2
103 #endif
104#endif
105
106#if (CONFIG_MEM_MT48LC16M16A2TG_75)
107 /*SDRAM INFORMATION: */
Aubrey Li8db13d62007-03-10 23:49:29 +0800[diff] [blame^]108 #define SDRAM_Tref 64 /* Refresh period in milliseconds */
109 #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100[diff] [blame]110 #define SDRAM_CL CL_3
111#endif
112
113#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
114 /*SDRAM INFORMATION: */
Aubrey Li8db13d62007-03-10 23:49:29 +0800[diff] [blame^]115 #define SDRAM_Tref 64 /* Refresh period in milliseconds */
116 #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100[diff] [blame]117 #define SDRAM_CL CL_2
118#endif
119
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800[diff] [blame]120#if (CONFIG_MEM_MT48LC16M8A2TG_75)
Aubrey Li8db13d62007-03-10 23:49:29 +0800[diff] [blame^]121 /*SDRAM INFORMATION: */
122 #define SDRAM_Tref 64 /* Refresh period in milliseconds */
123 #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
124 #define SDRAM_CL CL_3
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800[diff] [blame]125#endif
126
127#if (CONFIG_MEM_MT48LC32M8A2_75)
Aubrey Li8db13d62007-03-10 23:49:29 +0800[diff] [blame^]128/*SDRAM INFORMATION: */
129#define SDRAM_Tref 64 /* Refresh period in milliseconds */
130#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800[diff] [blame]131#define SDRAM_CL CL_3
132#endif
133
134#if (CONFIG_MEM_MT48LC8M16A2TG_7E)
135 /*SDRAM INFORMATION: */
Aubrey Li8db13d62007-03-10 23:49:29 +0800[diff] [blame^]136 #define SDRAM_Tref 64 /* Refresh period in milliseconds */
137 #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800[diff] [blame]138 #define SDRAM_CL CL_2
139#endif
140
141#if (CONFIG_MEM_MT48LC8M32B2B5_7)
142 /*SDRAM INFORMATION: */
Aubrey Li8db13d62007-03-10 23:49:29 +0800[diff] [blame^]143 #define SDRAM_Tref 64 /* Refresh period in milliseconds */
144 #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800[diff] [blame]145 #define SDRAM_CL CL_3
146#endif
147
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100[diff] [blame]148#if ( CONFIG_MEM_SIZE == 128 )
149 #define SDRAM_SIZE EBSZ_128
150#endif
151#if ( CONFIG_MEM_SIZE == 64 )
152 #define SDRAM_SIZE EBSZ_64
153#endif
154#if ( CONFIG_MEM_SIZE == 32 )
155 #define SDRAM_SIZE EBSZ_32
156#endif
157#if ( CONFIG_MEM_SIZE == 16 )
158 #define SDRAM_SIZE EBSZ_16
159#endif
160#if ( CONFIG_MEM_ADD_WDTH == 11 )
161 #define SDRAM_WIDTH EBCAW_11
162#endif
163#if ( CONFIG_MEM_ADD_WDTH == 10 )
164 #define SDRAM_WIDTH EBCAW_10
165#endif
166#if ( CONFIG_MEM_ADD_WDTH == 9 )
167 #define SDRAM_WIDTH EBCAW_9
168#endif
169#if ( CONFIG_MEM_ADD_WDTH == 8 )
170 #define SDRAM_WIDTH EBCAW_8
171#endif
172
173#define mem_SDBCTL SDRAM_WIDTH | SDRAM_SIZE | EBE
174
175/* Equation from section 17 (p17-46) of BF533 HRM */
176#define mem_SDRRC ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
177
178/* Enable SCLK Out */
179#define mem_SDGCTL ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS )
180
181#define flash_EBIU_AMBCTL_WAT ( ( CONFIG_FLASH_SPEED_BWAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
182#define flash_EBIU_AMBCTL_RAT ( ( CONFIG_FLASH_SPEED_BRAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
183#define flash_EBIU_AMBCTL_HT ( ( CONFIG_FLASH_SPEED_BHT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) )
184#define flash_EBIU_AMBCTL_ST ( ( CONFIG_FLASH_SPEED_BST * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
185#define flash_EBIU_AMBCTL_TT ( ( CONFIG_FLASH_SPEED_BTT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
186
187#if (flash_EBIU_AMBCTL_TT > 3 )
188 #define flash_EBIU_AMBCTL0_TT B0TT_4
189#endif
190#if (flash_EBIU_AMBCTL_TT == 3 )
191 #define flash_EBIU_AMBCTL0_TT B0TT_3
192#endif
193#if (flash_EBIU_AMBCTL_TT == 2 )
194 #define flash_EBIU_AMBCTL0_TT B0TT_2
195#endif
196#if (flash_EBIU_AMBCTL_TT < 2 )
197 #define flash_EBIU_AMBCTL0_TT B0TT_1
198#endif
199
200#if (flash_EBIU_AMBCTL_ST > 3 )
201 #define flash_EBIU_AMBCTL0_ST B0ST_4
202#endif
203#if (flash_EBIU_AMBCTL_ST == 3 )
204 #define flash_EBIU_AMBCTL0_ST B0ST_3
205#endif
206#if (flash_EBIU_AMBCTL_ST == 2 )
207 #define flash_EBIU_AMBCTL0_ST B0ST_2
208#endif
209#if (flash_EBIU_AMBCTL_ST < 2 )
210 #define flash_EBIU_AMBCTL0_ST B0ST_1
211#endif
212
213#if (flash_EBIU_AMBCTL_HT > 2 )
214 #define flash_EBIU_AMBCTL0_HT B0HT_3
215#endif
216#if (flash_EBIU_AMBCTL_HT == 2 )
217 #define flash_EBIU_AMBCTL0_HT B0HT_2
218#endif
219#if (flash_EBIU_AMBCTL_HT == 1 )
220 #define flash_EBIU_AMBCTL0_HT B0HT_1
221#endif
222#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
223 #define flash_EBIU_AMBCTL0_HT B0HT_0
224#endif
225#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
226 #define flash_EBIU_AMBCTL0_HT B0HT_1
227#endif
228
229#if (flash_EBIU_AMBCTL_WAT > 14)
230 #define flash_EBIU_AMBCTL0_WAT B0WAT_15
231#endif
232#if (flash_EBIU_AMBCTL_WAT == 14)
233 #define flash_EBIU_AMBCTL0_WAT B0WAT_14
234#endif
235#if (flash_EBIU_AMBCTL_WAT == 13)
236 #define flash_EBIU_AMBCTL0_WAT B0WAT_13
237#endif
238#if (flash_EBIU_AMBCTL_WAT == 12)
239 #define flash_EBIU_AMBCTL0_WAT B0WAT_12
240#endif
241#if (flash_EBIU_AMBCTL_WAT == 11)
242 #define flash_EBIU_AMBCTL0_WAT B0WAT_11
243#endif
244#if (flash_EBIU_AMBCTL_WAT == 10)
245 #define flash_EBIU_AMBCTL0_WAT B0WAT_10
246#endif
247#if (flash_EBIU_AMBCTL_WAT == 9)
248 #define flash_EBIU_AMBCTL0_WAT B0WAT_9
249#endif
250#if (flash_EBIU_AMBCTL_WAT == 8)
251 #define flash_EBIU_AMBCTL0_WAT B0WAT_8
252#endif
253#if (flash_EBIU_AMBCTL_WAT == 7)
254 #define flash_EBIU_AMBCTL0_WAT B0WAT_7
255#endif
256#if (flash_EBIU_AMBCTL_WAT == 6)
257 #define flash_EBIU_AMBCTL0_WAT B0WAT_6
258#endif
259#if (flash_EBIU_AMBCTL_WAT == 5)
260 #define flash_EBIU_AMBCTL0_WAT B0WAT_5
261#endif
262#if (flash_EBIU_AMBCTL_WAT == 4)
263 #define flash_EBIU_AMBCTL0_WAT B0WAT_4
264#endif
265#if (flash_EBIU_AMBCTL_WAT == 3)
266 #define flash_EBIU_AMBCTL0_WAT B0WAT_3
267#endif
268#if (flash_EBIU_AMBCTL_WAT == 2)
269 #define flash_EBIU_AMBCTL0_WAT B0WAT_2
270#endif
271#if (flash_EBIU_AMBCTL_WAT == 1)
272 #define flash_EBIU_AMBCTL0_WAT B0WAT_1
273#endif
274
275#if (flash_EBIU_AMBCTL_RAT > 14)
276 #define flash_EBIU_AMBCTL0_RAT B0RAT_15
277#endif
278#if (flash_EBIU_AMBCTL_RAT == 14)
279 #define flash_EBIU_AMBCTL0_RAT B0RAT_14
280#endif
281#if (flash_EBIU_AMBCTL_RAT == 13)
282 #define flash_EBIU_AMBCTL0_RAT B0RAT_13
283#endif
284#if (flash_EBIU_AMBCTL_RAT == 12)
285 #define flash_EBIU_AMBCTL0_RAT B0RAT_12
286#endif
287#if (flash_EBIU_AMBCTL_RAT == 11)
288 #define flash_EBIU_AMBCTL0_RAT B0RAT_11
289#endif
290#if (flash_EBIU_AMBCTL_RAT == 10)
291 #define flash_EBIU_AMBCTL0_RAT B0RAT_10
292#endif
293#if (flash_EBIU_AMBCTL_RAT == 9)
294 #define flash_EBIU_AMBCTL0_RAT B0RAT_9
295#endif
296#if (flash_EBIU_AMBCTL_RAT == 8)
297 #define flash_EBIU_AMBCTL0_RAT B0RAT_8
298#endif
299#if (flash_EBIU_AMBCTL_RAT == 7)
300 #define flash_EBIU_AMBCTL0_RAT B0RAT_7
301#endif
302#if (flash_EBIU_AMBCTL_RAT == 6)
303 #define flash_EBIU_AMBCTL0_RAT B0RAT_6
304#endif
305#if (flash_EBIU_AMBCTL_RAT == 5)
306 #define flash_EBIU_AMBCTL0_RAT B0RAT_5
307#endif
308#if (flash_EBIU_AMBCTL_RAT == 4)
309 #define flash_EBIU_AMBCTL0_RAT B0RAT_4
310#endif
311#if (flash_EBIU_AMBCTL_RAT == 3)
312 #define flash_EBIU_AMBCTL0_RAT B0RAT_3
313#endif
314#if (flash_EBIU_AMBCTL_RAT == 2)
315 #define flash_EBIU_AMBCTL0_RAT B0RAT_2
316#endif
317#if (flash_EBIU_AMBCTL_RAT == 1)
318 #define flash_EBIU_AMBCTL0_RAT B0RAT_1
319#endif
320
321#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN