| wdenk | 281e00a | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 1 | /* |
| 2 | * dm9000 Ethernet |
| 3 | */ |
| 4 | |
| 5 | #ifdef CONFIG_DRIVER_DM9000 |
| 6 | |
| 7 | #define DM9000_ID 0x90000A46 |
| 8 | #define DM9000_PKT_MAX 1536 /* Received packet max size */ |
| 9 | #define DM9000_PKT_RDY 0x01 /* Packet ready to receive */ |
| 10 | |
| 11 | /* although the registers are 16 bit, they are 32-bit aligned. |
| 12 | */ |
| 13 | |
| 14 | #define DM9000_NCR 0x00 |
| 15 | #define DM9000_NSR 0x01 |
| 16 | #define DM9000_TCR 0x02 |
| 17 | #define DM9000_TSR1 0x03 |
| 18 | #define DM9000_TSR2 0x04 |
| 19 | #define DM9000_RCR 0x05 |
| 20 | #define DM9000_RSR 0x06 |
| 21 | #define DM9000_ROCR 0x07 |
| 22 | #define DM9000_BPTR 0x08 |
| 23 | #define DM9000_FCTR 0x09 |
| 24 | #define DM9000_FCR 0x0A |
| 25 | #define DM9000_EPCR 0x0B |
| 26 | #define DM9000_EPAR 0x0C |
| 27 | #define DM9000_EPDRL 0x0D |
| 28 | #define DM9000_EPDRH 0x0E |
| 29 | #define DM9000_WCR 0x0F |
| 30 | |
| 31 | #define DM9000_PAR 0x10 |
| 32 | #define DM9000_MAR 0x16 |
| 33 | |
| 34 | #define DM9000_GPCR 0x1e |
| 35 | #define DM9000_GPR 0x1f |
| 36 | #define DM9000_TRPAL 0x22 |
| 37 | #define DM9000_TRPAH 0x23 |
| 38 | #define DM9000_RWPAL 0x24 |
| 39 | #define DM9000_RWPAH 0x25 |
| 40 | |
| 41 | #define DM9000_VIDL 0x28 |
| 42 | #define DM9000_VIDH 0x29 |
| 43 | #define DM9000_PIDL 0x2A |
| 44 | #define DM9000_PIDH 0x2B |
| 45 | |
| 46 | #define DM9000_CHIPR 0x2C |
| 47 | #define DM9000_SMCR 0x2F |
| 48 | |
| 49 | #define DM9000_PHY 0x40 /* PHY address 0x01 */ |
| 50 | |
| 51 | #define DM9000_MRCMDX 0xF0 |
| 52 | #define DM9000_MRCMD 0xF2 |
| 53 | #define DM9000_MRRL 0xF4 |
| 54 | #define DM9000_MRRH 0xF5 |
| 55 | #define DM9000_MWCMDX 0xF6 |
| 56 | #define DM9000_MWCMD 0xF8 |
| 57 | #define DM9000_MWRL 0xFA |
| 58 | #define DM9000_MWRH 0xFB |
| 59 | #define DM9000_TXPLL 0xFC |
| 60 | #define DM9000_TXPLH 0xFD |
| 61 | #define DM9000_ISR 0xFE |
| 62 | #define DM9000_IMR 0xFF |
| 63 | |
| 64 | #define NCR_EXT_PHY (1<<7) |
| 65 | #define NCR_WAKEEN (1<<6) |
| 66 | #define NCR_FCOL (1<<4) |
| 67 | #define NCR_FDX (1<<3) |
| 68 | #define NCR_LBK (3<<1) |
| 69 | #define NCR_RST (1<<0) |
| 70 | |
| 71 | #define NSR_SPEED (1<<7) |
| 72 | #define NSR_LINKST (1<<6) |
| 73 | #define NSR_WAKEST (1<<5) |
| 74 | #define NSR_TX2END (1<<3) |
| 75 | #define NSR_TX1END (1<<2) |
| 76 | #define NSR_RXOV (1<<1) |
| 77 | |
| 78 | #define TCR_TJDIS (1<<6) |
| 79 | #define TCR_EXCECM (1<<5) |
| 80 | #define TCR_PAD_DIS2 (1<<4) |
| 81 | #define TCR_CRC_DIS2 (1<<3) |
| 82 | #define TCR_PAD_DIS1 (1<<2) |
| 83 | #define TCR_CRC_DIS1 (1<<1) |
| 84 | #define TCR_TXREQ (1<<0) |
| 85 | |
| 86 | #define TSR_TJTO (1<<7) |
| 87 | #define TSR_LC (1<<6) |
| 88 | #define TSR_NC (1<<5) |
| 89 | #define TSR_LCOL (1<<4) |
| 90 | #define TSR_COL (1<<3) |
| 91 | #define TSR_EC (1<<2) |
| 92 | |
| 93 | #define RCR_WTDIS (1<<6) |
| 94 | #define RCR_DIS_LONG (1<<5) |
| 95 | #define RCR_DIS_CRC (1<<4) |
| 96 | #define RCR_ALL (1<<3) |
| 97 | #define RCR_RUNT (1<<2) |
| 98 | #define RCR_PRMSC (1<<1) |
| 99 | #define RCR_RXEN (1<<0) |
| 100 | |
| 101 | #define RSR_RF (1<<7) |
| 102 | #define RSR_MF (1<<6) |
| 103 | #define RSR_LCS (1<<5) |
| 104 | #define RSR_RWTO (1<<4) |
| 105 | #define RSR_PLE (1<<3) |
| 106 | #define RSR_AE (1<<2) |
| 107 | #define RSR_CE (1<<1) |
| 108 | #define RSR_FOE (1<<0) |
| 109 | |
| 110 | #define FCTR_HWOT(ot) (( ot & 0xf ) << 4 ) |
| 111 | #define FCTR_LWOT(ot) ( ot & 0xf ) |
| 112 | |
| 113 | #define IMR_PAR (1<<7) |
| 114 | #define IMR_ROOM (1<<3) |
| 115 | #define IMR_ROM (1<<2) |
| 116 | #define IMR_PTM (1<<1) |
| 117 | #define IMR_PRM (1<<0) |
| 118 | |
| 119 | #endif |