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Haiying Wang765547d2009-03-27 17:02:45 -04001/*
Kumar Gala6525d512010-07-08 22:37:44 -05002 * Copyright 2009-2010 Freescale Semiconductor.
Haiying Wang765547d2009-03-27 17:02:45 -04003 *
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
Anton Vorontsov7f52ed52009-10-15 17:47:06 +040026#include <hwconfig.h>
Haiying Wang765547d2009-03-27 17:02:45 -040027#include <pci.h>
28#include <asm/processor.h>
29#include <asm/mmu.h>
Haiying Wang3aed5502010-09-29 13:31:35 -040030#include <asm/cache.h>
Haiying Wang765547d2009-03-27 17:02:45 -040031#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050032#include <asm/fsl_pci.h>
Haiying Wang765547d2009-03-27 17:02:45 -040033#include <asm/fsl_ddr_sdram.h>
Kumar Gala5d27e022010-12-15 04:55:20 -060034#include <asm/fsl_serdes.h>
Haiying Wang765547d2009-03-27 17:02:45 -040035#include <asm/io.h>
36#include <spd_sdram.h>
37#include <i2c.h>
38#include <ioports.h>
39#include <libfdt.h>
40#include <fdt_support.h>
Anton Vorontsov7f52ed52009-10-15 17:47:06 +040041#include <fsl_esdhc.h>
Andy Fleming865ff852011-04-13 00:37:12 -050042#include <phy.h>
Haiying Wang765547d2009-03-27 17:02:45 -040043
44#include "bcsr.h"
Liu Yud9180382009-11-27 15:31:51 +080045#if defined(CONFIG_PQ_MDS_PIB)
46#include "../common/pq-mds-pib.h"
47#endif
Haiying Wang765547d2009-03-27 17:02:45 -040048
Haiying Wang765547d2009-03-27 17:02:45 -040049const qe_iop_conf_t qe_iop_conf_tab[] = {
50 /* QE_MUX_MDC */
51 {2, 31, 1, 0, 1}, /* QE_MUX_MDC */
52
53 /* QE_MUX_MDIO */
54 {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
55
Haiying Wangf82107f2009-05-20 12:30:37 -040056#if defined(CONFIG_SYS_UCC_RGMII_MODE)
Haiying Wang765547d2009-03-27 17:02:45 -040057 /* UCC_1_RGMII */
58 {2, 11, 2, 0, 1}, /* CLK12 */
59 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
60 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
61 {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
62 {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
63 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
64 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
65 {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
66 {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
67 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
68 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
69 {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
70 {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
71
72 /* UCC_2_RGMII */
73 {2, 16, 2, 0, 3}, /* CLK17 */
74 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
75 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
76 {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
77 {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
78 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
79 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
80 {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
81 {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
82 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
83 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
84 {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
85 {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
86
Haiying Wang750098d2009-05-20 12:30:36 -040087 /* UCC_3_RGMII */
88 {2, 11, 2, 0, 1}, /* CLK12 */
89 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
90 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
91 {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
92 {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
93 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
94 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
95 {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
96 {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
97 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
98 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
99 {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
100 {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
101
102 /* UCC_4_RGMII */
103 {2, 16, 2, 0, 3}, /* CLK17 */
104 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
105 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
106 {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
107 {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
108 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
109 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
110 {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
111 {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
112 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
113 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
114 {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
115 {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
116
Haiying Wangf82107f2009-05-20 12:30:37 -0400117#elif defined(CONFIG_SYS_UCC_RMII_MODE)
118 /* UCC_1_RMII */
119 {2, 15, 2, 0, 1}, /* CLK16 */
120 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
121 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
122 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
123 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
124 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
125 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
126
127 /* UCC_2_RMII */
128 {2, 15, 2, 0, 1}, /* CLK16 */
129 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
130 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
131 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
132 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
133 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
134 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
135
136 /* UCC_3_RMII */
137 {2, 15, 2, 0, 1}, /* CLK16 */
138 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
139 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
140 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
141 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
142 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
143 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
144
145 /* UCC_4_RMII */
146 {2, 15, 2, 0, 1}, /* CLK16 */
147 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
148 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
149 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
150 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
151 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
152 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
153#endif
154
Haiying Wangb2aab382009-05-20 12:30:33 -0400155 /* UART1 is muxed with QE PortF bit [9-12].*/
156 {5, 12, 2, 0, 3}, /* UART1_SIN */
157 {5, 9, 1, 0, 3}, /* UART1_SOUT */
158 {5, 10, 2, 0, 3}, /* UART1_CTS_B */
159 {5, 11, 1, 0, 2}, /* UART1_RTS_B */
160
Anton Vorontsov14809b62009-10-15 17:47:13 +0400161 /* QE UART */
162 {0, 19, 1, 0, 2}, /* QEUART_TX */
163 {1, 17, 2, 0, 3}, /* QEUART_RX */
164 {0, 25, 1, 0, 1}, /* QEUART_RTS */
165 {1, 23, 2, 0, 1}, /* QEUART_CTS */
166
Anton Vorontsov3fca8032009-10-15 17:47:16 +0400167 /* QE USB */
168 {5, 3, 1, 0, 1}, /* USB_OE */
169 {5, 4, 1, 0, 2}, /* USB_TP */
170 {5, 5, 1, 0, 2}, /* USB_TN */
171 {5, 6, 2, 0, 2}, /* USB_RP */
172 {5, 7, 2, 0, 1}, /* USB_RX */
173 {5, 8, 2, 0, 1}, /* USB_RN */
174 {2, 4, 2, 0, 2}, /* CLK5 */
175
Anton Vorontsov70d665b2009-10-15 17:47:11 +0400176 /* SPI Flash, M25P40 */
177 {4, 27, 3, 0, 1}, /* SPI_MOSI */
178 {4, 28, 3, 0, 1}, /* SPI_MISO */
179 {4, 29, 3, 0, 1}, /* SPI_CLK */
180 {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
181
Haiying Wang765547d2009-03-27 17:02:45 -0400182 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
183};
184
185void local_bus_init(void);
186
187int board_early_init_f (void)
188{
189 /*
190 * Initialize local bus.
191 */
192 local_bus_init ();
193
194 enable_8569mds_flash_write();
195
196#ifdef CONFIG_QE
Haiying Wangf82107f2009-05-20 12:30:37 -0400197 enable_8569mds_qe_uec();
Haiying Wang765547d2009-03-27 17:02:45 -0400198#endif
199
200#if CONFIG_SYS_I2C2_OFFSET
201 /* Enable I2C2 signals instead of SD signals */
202 volatile struct ccsr_gur *gur;
203 gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
204 gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
205 gur->plppar1 |= PLPPAR1_I2C2_VAL;
206 gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
207 gur->plpdir1 |= PLPDIR1_I2C2_VAL;
208
209 disable_8569mds_brd_eeprom_write_protect();
210#endif
211
212 return 0;
213}
214
Haiying Wang3aed5502010-09-29 13:31:35 -0400215int board_early_init_r(void)
216{
217 const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
218 const u8 flash_esel = 0;
219
220 /*
221 * Remap Boot flash to caching-inhibited
222 * so that flash can be erased properly.
223 */
224
225 /* Flush d-cache and invalidate i-cache of any FLASH data */
226 flush_dcache();
227 invalidate_icache();
228
229 /* invalidate existing TLB entry for flash */
230 disable_tlb(flash_esel);
231
232 set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
233 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
234 0, flash_esel, /* ts, esel */
235 BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
236
237 return 0;
238}
239
Haiying Wang765547d2009-03-27 17:02:45 -0400240int checkboard (void)
241{
242 printf ("Board: 8569 MDS\n");
243
244 return 0;
245}
246
Haiying Wang765547d2009-03-27 17:02:45 -0400247#if !defined(CONFIG_SPD_EEPROM)
248phys_size_t fixed_sdram(void)
249{
250 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
251 uint d_init;
252
253 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
254 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
255 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
256 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
257 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
258 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
259 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
260 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
261 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
262 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
263 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
264 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
265 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
266 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
267 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
268 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
269 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
270 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
271#if defined (CONFIG_DDR_ECC)
272 out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
273 out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
274 out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
275#endif
276 udelay(500);
277
278 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
279#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
280 d_init = 1;
281 debug("DDR - 1st controller: memory initializing\n");
282 /*
283 * Poll until memory is initialized.
284 * 512 Meg at 400 might hit this 200 times or so.
285 */
286 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
287 udelay(1000);
288 }
289 debug("DDR: memory initialized\n\n");
290 udelay(500);
291#endif
292 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
293}
294#endif
295
296/*
297 * Initialize Local Bus
298 */
299void
300local_bus_init(void)
301{
302 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Becky Brucef51cdaf2010-06-17 11:37:20 -0500303 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Haiying Wang765547d2009-03-27 17:02:45 -0400304
305 uint clkdiv;
Haiying Wang765547d2009-03-27 17:02:45 -0400306 sys_info_t sysinfo;
307
308 get_sys_info(&sysinfo);
309 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
Haiying Wang765547d2009-03-27 17:02:45 -0400310
311 out_be32(&gur->lbiuiplldcr1, 0x00078080);
312 if (clkdiv == 16)
313 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
314 else if (clkdiv == 8)
315 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
316 else if (clkdiv == 4)
317 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
318
319 out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
320}
321
Anton Vorontsov14809b62009-10-15 17:47:13 +0400322static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
323{
324 const char *status = "disabled";
325 int off;
326 int err;
327
328 off = fdt_path_offset(blob, alias);
329 if (off < 0) {
330 printf("WARNING: could not find %s alias: %s.\n", alias,
331 fdt_strerror(off));
332 return;
333 }
334
335 err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
336 if (err) {
337 printf("WARNING: could not set status for serial0: %s.\n",
338 fdt_strerror(err));
339 return;
340 }
341}
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400342
343/*
344 * Because of an erratum in prototype boards it is impossible to use eSDHC
345 * without disabling UART0 (which makes it quite easy to 'brick' the board
346 * by simply issung 'setenv hwconfig esdhc', and not able to interact with
347 * U-Boot anylonger).
348 *
349 * So, but default we assume that the board is a prototype, which is a most
350 * safe assumption. There is no way to determine board revision from a
351 * register, so we use hwconfig.
352 */
353
354static int prototype_board(void)
355{
356 if (hwconfig_subarg("board", "rev", NULL))
357 return hwconfig_subarg_cmp("board", "rev", "prototype");
358 return 1;
359}
360
361static int esdhc_disables_uart0(void)
362{
363 return prototype_board() ||
364 hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
365}
366
Anton Vorontsov14809b62009-10-15 17:47:13 +0400367static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
368{
369 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
370 const char *devtype = "serial";
371 const char *compat = "ucc_uart";
372 const char *clk = "brg9";
373 u32 portnum = 0;
374 int off = -1;
375
376 if (!hwconfig("qe_uart"))
377 return;
378
379 if (hwconfig("esdhc") && esdhc_disables_uart0()) {
380 printf("QE UART: won't enable with esdhc.\n");
381 return;
382 }
383
384 fdt_board_disable_serial(blob, bd, "serial1");
385
386 while (1) {
387 const u32 *idx;
388 int len;
389
390 off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
391 if (off < 0) {
392 printf("WARNING: unable to fixup device tree for "
393 "QE UART\n");
394 return;
395 }
396
397 idx = fdt_getprop(blob, off, "cell-index", &len);
398 if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
399 continue;
400 break;
401 }
402
403 fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
404 fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
405 fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
406 fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
407 fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
408
409 setbits_8(&bcsr[15], BCSR15_QEUART_EN);
410}
411
412#ifdef CONFIG_FSL_ESDHC
413
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400414int board_mmc_init(bd_t *bd)
415{
416 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
417 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
418 u8 bcsr6 = BCSR6_SD_CARD_1BIT;
419
420 if (!hwconfig("esdhc"))
421 return 0;
422
423 printf("Enabling eSDHC...\n"
424 " For eSDHC to function, I2C2 ");
425 if (esdhc_disables_uart0()) {
426 printf("and UART0 should be disabled.\n");
427 printf(" Redirecting stderr, stdout and stdin to UART1...\n");
428 console_assign(stderr, "eserial1");
429 console_assign(stdout, "eserial1");
430 console_assign(stdin, "eserial1");
431 printf("Switched to UART1 (initial log has been printed to "
432 "UART0).\n");
Anton Vorontsovc4ca10f2009-12-16 01:14:31 +0300433
434 clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
435 PLPPAR1_ESDHC_4BITS_VAL);
436 clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
437 PLPDIR1_ESDHC_4BITS_VAL);
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400438 bcsr6 |= BCSR6_SD_CARD_4BITS;
439 } else {
440 printf("should be disabled.\n");
441 }
442
443 /* Assign I2C2 signals to eSDHC. */
444 clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
445 PLPPAR1_ESDHC_VAL);
446 clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
447 PLPDIR1_ESDHC_VAL);
448
449 /* Mux I2C2 (and optionally UART0) signals to eSDHC. */
450 setbits_8(&bcsr[6], bcsr6);
451
452 return fsl_esdhc_mmc_init(bd);
453}
454
455static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
456{
457 const char *status = "disabled";
Anton Vorontsov14809b62009-10-15 17:47:13 +0400458 int off = -1;
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400459
460 if (!hwconfig("esdhc"))
461 return;
462
Anton Vorontsov14809b62009-10-15 17:47:13 +0400463 if (esdhc_disables_uart0())
464 fdt_board_disable_serial(blob, bd, "serial0");
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400465
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400466 while (1) {
467 const u32 *idx;
468 int len;
469
470 off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
471 if (off < 0)
472 break;
473
474 idx = fdt_getprop(blob, off, "cell-index", &len);
475 if (!idx || len != sizeof(*idx))
476 continue;
477
478 if (*idx == 1) {
479 fdt_setprop(blob, off, "status", status,
480 strlen(status) + 1);
481 break;
482 }
483 }
Anton Vorontsovc4ca10f2009-12-16 01:14:31 +0300484
485 if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
486 off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
487 if (off < 0) {
488 printf("WARNING: could not find esdhc node\n");
489 return;
490 }
491 fdt_delprop(blob, off, "sdhci,1-bit-only");
492 }
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400493}
494#else
495static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
496#endif
497
Anton Vorontsov3fca8032009-10-15 17:47:16 +0400498static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
499{
500 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
501
502 if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
503 clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
504 else
505 setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
506
507 if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
508 clrbits_8(&bcsr[17], BCSR17_USBVCC);
509 clrbits_8(&bcsr[17], BCSR17_USBMODE);
510 do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
511 "peripheral", sizeof("peripheral"), 1);
512 } else {
513 setbits_8(&bcsr[17], BCSR17_USBVCC);
514 setbits_8(&bcsr[17], BCSR17_USBMODE);
515 }
516
517 clrbits_8(&bcsr[17], BCSR17_nUSBEN);
518}
519
Haiying Wang765547d2009-03-27 17:02:45 -0400520#ifdef CONFIG_PCI
Kumar Galac847e982009-11-04 10:26:30 -0600521void pci_init_board(void)
Haiying Wang765547d2009-03-27 17:02:45 -0400522{
Liu Yud9180382009-11-27 15:31:51 +0800523#if defined(CONFIG_PQ_MDS_PIB)
524 pib_init();
525#endif
526
Kumar Gala94f2bc42010-12-17 10:18:07 -0600527 fsl_pcie_init_board(0);
Haiying Wang765547d2009-03-27 17:02:45 -0400528}
529#endif /* CONFIG_PCI */
530
531#if defined(CONFIG_OF_BOARD_SETUP)
Haiying Wang765547d2009-03-27 17:02:45 -0400532void ft_board_setup(void *blob, bd_t *bd)
533{
Haiying Wangf82107f2009-05-20 12:30:37 -0400534#if defined(CONFIG_SYS_UCC_RMII_MODE)
535 int nodeoff, off, err;
536 unsigned int val;
537 const u32 *ph;
538 const u32 *index;
539
540 /* fixup device tree for supporting rmii mode */
541 nodeoff = -1;
542 while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
543 "ucc_geth")) >= 0) {
544 err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
545 "clk16");
546 if (err < 0) {
547 printf("WARNING: could not set tx-clock-name %s.\n",
548 fdt_strerror(err));
549 break;
550 }
551
Andy Fleming865ff852011-04-13 00:37:12 -0500552 err = fdt_fixup_phy_connection(blob, nodeoff,
553 PHY_INTERFACE_MODE_RMII);
Kumar Galaa1964ea2010-09-30 09:15:03 -0500554
Haiying Wangf82107f2009-05-20 12:30:37 -0400555 if (err < 0) {
556 printf("WARNING: could not set phy-connection-type "
557 "%s.\n", fdt_strerror(err));
558 break;
559 }
560
561 index = fdt_getprop(blob, nodeoff, "cell-index", 0);
562 if (index == NULL) {
563 printf("WARNING: could not get cell-index of ucc\n");
564 break;
565 }
566
567 ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
568 if (ph == NULL) {
569 printf("WARNING: could not get phy-handle of ucc\n");
570 break;
571 }
572
573 off = fdt_node_offset_by_phandle(blob, *ph);
574 if (off < 0) {
575 printf("WARNING: could not get phy node %s.\n",
576 fdt_strerror(err));
577 break;
578 }
579
580 val = 0x7 + *index; /* RMII phy address starts from 0x8 */
581
582 err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
583 if (err < 0) {
584 printf("WARNING: could not set reg for phy-handle "
585 "%s.\n", fdt_strerror(err));
586 break;
587 }
588 }
589#endif
Haiying Wang765547d2009-03-27 17:02:45 -0400590 ft_cpu_setup(blob, bd);
591
Kumar Gala6525d512010-07-08 22:37:44 -0500592 FT_FSL_PCI_SETUP;
593
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400594 fdt_board_fixup_esdhc(blob, bd);
Anton Vorontsov14809b62009-10-15 17:47:13 +0400595 fdt_board_fixup_qe_uart(blob, bd);
Anton Vorontsov3fca8032009-10-15 17:47:16 +0400596 fdt_board_fixup_qe_usb(blob, bd);
Haiying Wang765547d2009-03-27 17:02:45 -0400597}
598#endif