blob: 423e9d72a761b56b8b024c1190fc832a411a354f [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk97d80fc2004-06-09 00:34:46 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2003,Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27
wdenk42d1f032003-10-15 23:53:47 +000028#include <common.h>
wdenk9aea9532004-08-01 23:02:45 +000029#include <pci.h>
wdenk42d1f032003-10-15 23:53:47 +000030#include <asm/processor.h>
Jon Loeliger8b625112008-03-18 11:12:44 -050031#include <asm/mmu.h>
wdenk42d1f032003-10-15 23:53:47 +000032#include <asm/immap_85xx.h>
Jon Loeliger8b625112008-03-18 11:12:44 -050033#include <asm/fsl_ddr_sdram.h>
wdenk42d1f032003-10-15 23:53:47 +000034#include <ioports.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060035#include <spd_sdram.h>
wdenk42d1f032003-10-15 23:53:47 +000036#include <miiphy.h>
Kumar Gala5ce71582007-11-28 22:40:31 -060037#include <libfdt.h>
38#include <fdt_support.h>
Kumar Galab0fe93ed2009-03-26 01:34:38 -050039#include <asm/fsl_lbc.h>
Jon Loeligerf5012822006-10-20 15:54:34 -050040
Jon Loeligerd9b94f22005-07-25 14:05:07 -050041#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk0ac6f8b2004-07-09 23:27:13 +000042extern void ddr_enable_ecc(unsigned int dram_size);
43#endif
44
wdenk0ac6f8b2004-07-09 23:27:13 +000045
wdenk9aea9532004-08-01 23:02:45 +000046void local_bus_init(void);
wdenk0ac6f8b2004-07-09 23:27:13 +000047void sdram_init(void);
48long int fixed_sdram(void);
49
wdenk42d1f032003-10-15 23:53:47 +000050
51/*
52 * I/O Port configuration table
53 *
54 * if conf is 1, then that port pin will be configured at boot time
55 * according to the five values podr/pdir/ppar/psor/pdat for that entry
56 */
57
58const iop_conf_t iop_conf_tab[4][32] = {
59
60 /* Port A configuration */
61 { /* conf ppar psor pdir podr pdat */
62 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
63 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
64 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
65 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
66 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
67 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
68 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
69 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
70 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
71 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
72 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
73 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
74 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
75 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
76 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
77 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
78 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
79 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
80 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
81 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
82 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
83 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
84 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
85 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
86 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
87 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
88 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
89 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
90 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
91 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
92 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
93 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
94 },
95
96 /* Port B configuration */
97 { /* conf ppar psor pdir podr pdat */
98 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
99 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
100 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
101 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
102 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
103 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
104 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
105 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
106 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
107 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
108 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
109 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
110 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
111 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
112 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
113 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
114 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
115 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
116 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
117 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
118 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
119 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
120 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
121 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
122 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
123 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
124 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
125 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
126 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
127 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
128 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
129 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
130 },
131
132 /* Port C */
133 { /* conf ppar psor pdir podr pdat */
134 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
135 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
136 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
137 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
138 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
139 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
140 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
141 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
142 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
143 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
144 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
145 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
146 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
147 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
148 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
149 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
150 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
151 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
152 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
153 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
154 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
155 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
156 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
157 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
158 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
159 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
160 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
161 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
162 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
163 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
164 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
165 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
166 },
167
168 /* Port D */
169 { /* conf ppar psor pdir podr pdat */
170 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
171 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
172 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
173 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
174 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
175 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
176 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
177 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
178 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
179 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
180 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
181 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
182 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
183 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
184 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
185 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
186 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
187 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
188 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
189 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
190 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
191 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
192 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
193 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
194 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
195 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
196 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
197 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
198 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
199 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
200 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
201 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
202 }
203};
204
wdenk0ac6f8b2004-07-09 23:27:13 +0000205
206/*
207 * MPC8560ADS Board Status & Control Registers
208 */
209typedef struct bcsr_ {
wdenk42d1f032003-10-15 23:53:47 +0000210 volatile unsigned char bcsr0;
211 volatile unsigned char bcsr1;
212 volatile unsigned char bcsr2;
213 volatile unsigned char bcsr3;
214 volatile unsigned char bcsr4;
215 volatile unsigned char bcsr5;
216} bcsr_t;
217
wdenk42d1f032003-10-15 23:53:47 +0000218void reset_phy (void)
219{
220#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221 volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR;
wdenk42d1f032003-10-15 23:53:47 +0000222#endif
223 /* reset Giga bit Ethernet port if needed here */
224
225 /* reset the CPM FEC port */
226#if (CONFIG_ETHER_INDEX == 2)
227 bcsr->bcsr2 &= ~FETH2_RST;
228 udelay(2);
229 bcsr->bcsr2 |= FETH2_RST;
230 udelay(1000);
231#elif (CONFIG_ETHER_INDEX == 3)
232 bcsr->bcsr3 &= ~FETH3_RST;
233 udelay(2);
234 bcsr->bcsr3 |= FETH3_RST;
235 udelay(1000);
236#endif
237#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200238 /* reset PHY */
Heiko Schocher48690d82010-07-20 17:45:02 +0200239 miiphy_reset("FCC1", 0x0);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200240
241 /* change PHY address to 0x02 */
242 bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
243
244 bb_miiphy_write(NULL, 0x02, PHY_BMCR,
245 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
wdenk42d1f032003-10-15 23:53:47 +0000246#endif /* CONFIG_MII */
247}
248
wdenk9aea9532004-08-01 23:02:45 +0000249
wdenk42d1f032003-10-15 23:53:47 +0000250int checkboard (void)
251{
wdenk97d80fc2004-06-09 00:34:46 +0000252 puts("Board: ADS\n");
wdenk0ac6f8b2004-07-09 23:27:13 +0000253
254#ifdef CONFIG_PCI
255 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
256 CONFIG_SYS_CLK_FREQ / 1000000);
257#else
258 printf(" PCI1: disabled\n");
259#endif
wdenk9aea9532004-08-01 23:02:45 +0000260
261 /*
262 * Initialize local bus.
263 */
264 local_bus_init();
265
wdenk97d80fc2004-06-09 00:34:46 +0000266 return 0;
wdenk42d1f032003-10-15 23:53:47 +0000267}
268
269
Becky Bruce9973e3c2008-06-09 16:03:40 -0500270phys_size_t
wdenk0ac6f8b2004-07-09 23:27:13 +0000271initdram(int board_type)
wdenk42d1f032003-10-15 23:53:47 +0000272{
273 long dram_size = 0;
wdenk0ac6f8b2004-07-09 23:27:13 +0000274
275 puts("Initializing\n");
wdenk97d80fc2004-06-09 00:34:46 +0000276
wdenk42d1f032003-10-15 23:53:47 +0000277#if defined(CONFIG_DDR_DLL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000278 {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
wdenk9aea9532004-08-01 23:02:45 +0000280 uint temp_ddrdll = 0;
wdenk42d1f032003-10-15 23:53:47 +0000281
wdenk9aea9532004-08-01 23:02:45 +0000282 /*
283 * Work around to stabilize DDR DLL
284 */
285 temp_ddrdll = gur->ddrdllcr;
286 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
287 asm("sync;isync;msync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000288 }
wdenk42d1f032003-10-15 23:53:47 +0000289#endif
290
Jon Loeliger8b625112008-03-18 11:12:44 -0500291#ifdef CONFIG_SPD_EEPROM
292 dram_size = fsl_ddr_sdram();
293 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
294
295 dram_size *= 0x100000;
wdenk42d1f032003-10-15 23:53:47 +0000296#else
Jon Loeliger8b625112008-03-18 11:12:44 -0500297 dram_size = fixed_sdram();
wdenk42d1f032003-10-15 23:53:47 +0000298#endif
299
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500300#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk0ac6f8b2004-07-09 23:27:13 +0000301 /*
302 * Initialize and enable DDR ECC.
303 */
304 ddr_enable_ecc(dram_size);
305#endif
306
307 /*
308 * Initialize SDRAM.
309 */
310 sdram_init();
311
312 puts(" DDR: ");
313 return dram_size;
314}
315
316
317/*
wdenk9aea9532004-08-01 23:02:45 +0000318 * Initialize Local Bus
wdenk0ac6f8b2004-07-09 23:27:13 +0000319 */
320
wdenk9aea9532004-08-01 23:02:45 +0000321void
322local_bus_init(void)
wdenk0ac6f8b2004-07-09 23:27:13 +0000323{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Becky Brucef51cdaf2010-06-17 11:37:20 -0500325 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
wdenk0ac6f8b2004-07-09 23:27:13 +0000326
wdenk9aea9532004-08-01 23:02:45 +0000327 uint clkdiv;
328 uint lbc_hz;
329 sys_info_t sysinfo;
wdenk0ac6f8b2004-07-09 23:27:13 +0000330
331 /*
wdenk9aea9532004-08-01 23:02:45 +0000332 * Errata LBC11.
333 * Fix Local Bus clock glitch when DLL is enabled.
wdenk0ac6f8b2004-07-09 23:27:13 +0000334 *
Wolfgang Denk8ed44d92008-10-19 02:35:50 +0200335 * If localbus freq is < 66MHz, DLL bypass mode must be used.
336 * If localbus freq is > 133MHz, DLL can be safely enabled.
wdenk9aea9532004-08-01 23:02:45 +0000337 * Between 66 and 133, the DLL is enabled with an override workaround.
wdenk0ac6f8b2004-07-09 23:27:13 +0000338 */
wdenk9aea9532004-08-01 23:02:45 +0000339
340 get_sys_info(&sysinfo);
Trent Piephoa5d212a2008-12-03 15:16:34 -0800341 clkdiv = lbc->lcrr & LCRR_CLKDIV;
wdenk9aea9532004-08-01 23:02:45 +0000342 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
343
344 if (lbc_hz < 66) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345 lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */
wdenk9aea9532004-08-01 23:02:45 +0000346
347 } else if (lbc_hz >= 133) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
wdenk0ac6f8b2004-07-09 23:27:13 +0000349
wdenk42d1f032003-10-15 23:53:47 +0000350 } else {
wdenk0ac6f8b2004-07-09 23:27:13 +0000351 /*
352 * On REV1 boards, need to change CLKDIV before enable DLL.
353 * Default CLKDIV is 8, change it to 4 temporarily.
354 */
wdenk9aea9532004-08-01 23:02:45 +0000355 uint pvr = get_pvr();
wdenk0ac6f8b2004-07-09 23:27:13 +0000356 uint temp_lbcdll = 0;
wdenk97d80fc2004-06-09 00:34:46 +0000357
358 if (pvr == PVR_85xx_REV1) {
wdenk9aea9532004-08-01 23:02:45 +0000359 /* FIXME: Justify the high bit here. */
wdenk0ac6f8b2004-07-09 23:27:13 +0000360 lbc->lcrr = 0x10000004;
wdenk97d80fc2004-06-09 00:34:46 +0000361 }
wdenk0ac6f8b2004-07-09 23:27:13 +0000362
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */
wdenk9aea9532004-08-01 23:02:45 +0000364 udelay(200);
365
366 /*
367 * Sample LBC DLL ctrl reg, upshift it to set the
368 * override bits.
369 */
wdenk42d1f032003-10-15 23:53:47 +0000370 temp_lbcdll = gur->lbcdllcr;
wdenk9aea9532004-08-01 23:02:45 +0000371 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
372 asm("sync;isync;msync");
wdenk42d1f032003-10-15 23:53:47 +0000373 }
wdenk9aea9532004-08-01 23:02:45 +0000374}
375
376
377/*
378 * Initialize SDRAM memory on the Local Bus.
379 */
380
381void
382sdram_init(void)
383{
Becky Brucef51cdaf2010-06-17 11:37:20 -0500384 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
wdenk9aea9532004-08-01 23:02:45 +0000386
387 puts(" SDRAM: ");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
wdenk0ac6f8b2004-07-09 23:27:13 +0000389
390 /*
391 * Setup SDRAM Base and Option Registers
392 */
Becky Brucef51cdaf2010-06-17 11:37:20 -0500393 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
394 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
wdenk9aea9532004-08-01 23:02:45 +0000396 asm("msync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000397
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
399 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
wdenk9aea9532004-08-01 23:02:45 +0000400 asm("sync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000401
402 /*
403 * Configure the SDRAM controller.
404 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
wdenk9aea9532004-08-01 23:02:45 +0000406 asm("sync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000407 *sdram_addr = 0xff;
wdenk9aea9532004-08-01 23:02:45 +0000408 ppcDcbf((unsigned long) sdram_addr);
409 udelay(100);
wdenk0ac6f8b2004-07-09 23:27:13 +0000410
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
wdenk9aea9532004-08-01 23:02:45 +0000412 asm("sync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000413 *sdram_addr = 0xff;
wdenk9aea9532004-08-01 23:02:45 +0000414 ppcDcbf((unsigned long) sdram_addr);
415 udelay(100);
wdenk0ac6f8b2004-07-09 23:27:13 +0000416
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
wdenk9aea9532004-08-01 23:02:45 +0000418 asm("sync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000419 *sdram_addr = 0xff;
wdenk9aea9532004-08-01 23:02:45 +0000420 ppcDcbf((unsigned long) sdram_addr);
421 udelay(100);
wdenk0ac6f8b2004-07-09 23:27:13 +0000422
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
wdenk9aea9532004-08-01 23:02:45 +0000424 asm("sync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000425 *sdram_addr = 0xff;
wdenk9aea9532004-08-01 23:02:45 +0000426 ppcDcbf((unsigned long) sdram_addr);
427 udelay(100);
wdenk0ac6f8b2004-07-09 23:27:13 +0000428
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
wdenk9aea9532004-08-01 23:02:45 +0000430 asm("sync");
wdenk0ac6f8b2004-07-09 23:27:13 +0000431 *sdram_addr = 0xff;
wdenk9aea9532004-08-01 23:02:45 +0000432 ppcDcbf((unsigned long) sdram_addr);
433 udelay(100);
wdenk42d1f032003-10-15 23:53:47 +0000434}
435
wdenk42d1f032003-10-15 23:53:47 +0000436#if !defined(CONFIG_SPD_EEPROM)
437/*************************************************************************
438 * fixed sdram init -- doesn't use serial presence detect.
439 ************************************************************************/
440long int fixed_sdram (void)
441{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442 #ifndef CONFIG_SYS_RAMBOOT
443 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
446 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
447 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
448 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
449 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
450 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
wdenk42d1f032003-10-15 23:53:47 +0000451 #if defined (CONFIG_DDR_ECC)
452 ddr->err_disable = 0x0000000D;
453 ddr->err_sbe = 0x00ff0000;
454 #endif
455 asm("sync;isync;msync");
456 udelay(500);
457 #if defined (CONFIG_DDR_ECC)
458 /* Enable ECC checking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
wdenk42d1f032003-10-15 23:53:47 +0000460 #else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
wdenk42d1f032003-10-15 23:53:47 +0000462 #endif
463 asm("sync; isync; msync");
464 udelay(500);
465 #endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
wdenk42d1f032003-10-15 23:53:47 +0000467}
468#endif /* !defined(CONFIG_SPD_EEPROM) */
wdenk9aea9532004-08-01 23:02:45 +0000469
470
471#if defined(CONFIG_PCI)
472/*
473 * Initialize PCI Devices, report devices found.
474 */
475
476#ifndef CONFIG_PCI_PNP
477static struct pci_config_table pci_mpc85xxads_config_table[] = {
478 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
479 PCI_IDSEL_NUMBER, PCI_ANY_ID,
480 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
481 PCI_ENET0_MEMADDR,
482 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
483 } },
484 { }
485};
486#endif
487
488
489static struct pci_controller hose = {
490#ifndef CONFIG_PCI_PNP
491 config_table: pci_mpc85xxads_config_table,
492#endif
493};
494
495#endif /* CONFIG_PCI */
496
497
498void
499pci_init_board(void)
500{
501#ifdef CONFIG_PCI
wdenk9aea9532004-08-01 23:02:45 +0000502 pci_mpc85xx_init(&hose);
503#endif /* CONFIG_PCI */
504}
Matthew McClintock0e163872006-06-28 10:43:36 -0500505
506
Kumar Gala5ce71582007-11-28 22:40:31 -0600507#if defined(CONFIG_OF_BOARD_SETUP)
Andy Flemingccc091a2007-05-08 17:27:43 -0500508void
Matthew McClintock0e163872006-06-28 10:43:36 -0500509ft_board_setup(void *blob, bd_t *bd)
510{
Kumar Gala5ce71582007-11-28 22:40:31 -0600511 int node, tmp[2];
512 const char *path;
513
Matthew McClintock0e163872006-06-28 10:43:36 -0500514 ft_cpu_setup(blob, bd);
Kumar Gala5ce71582007-11-28 22:40:31 -0600515
516 node = fdt_path_offset(blob, "/aliases");
517 tmp[0] = 0;
518 if (node >= 0) {
519#ifdef CONFIG_PCI
520 path = fdt_getprop(blob, node, "pci0", NULL);
521 if (path) {
522 tmp[1] = hose.last_busno - hose.first_busno;
523 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
524 }
525#endif
526 }
Matthew McClintock0e163872006-06-28 10:43:36 -0500527}
528#endif