| commit | a72dbae2ccd38d2b32f8b814f5a528c88be65bd3 | [log] [tgz] |
|---|---|---|
| author | Peter Tyser <ptyser@xes-inc.com> | Thu Oct 28 15:24:59 2010 -0500 |
| committer | Wolfgang Denk <wd@denx.de> | Sun Nov 14 23:45:57 2010 +0100 |
| tree | 59d540d16474f386d3600fc5d0f9fdceff21c7da | |
| parent | 258ccd68170b7279ec7d4805c7b914c90374e711 [diff] |
fsl_pci_init: Make fsl_pci_init_port() PCI/PCIe aware
Previously fsl_pci_init_port() always assumed that a port was a PCIe
port and would incorrectly print messages for a PCI port such as the
following on bootup:
PCI1: 32 bit, 33 MHz, sync, host, arbiter
Scanning PCI bus 00
PCIE1 on bus 00 - 00
This change corrects the output of fsl_pci_init_port():
PCI1: 32 bit, 33 MHz, sync, host, arbiter
Scanning PCI bus 00
PCI1 on bus 00 - 00
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>