blob: 6f9eeb22f896b3ffc01c986ce0b7d9a89d2736eb [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <mpc824x.h>
26#include <pci.h>
Ben Warren8ca0b3f2008-08-31 10:45:44 -070027#include <netdev.h>
wdenkc6097192002-11-03 00:24:07 +000028
29int checkboard (void)
30{
31 ulong busfreq = get_bus_freq(0);
32 char buf[32];
33
34 printf("Board: MUSENKI Local Bus at %s MHz\n", strmhz(buf, busfreq));
35 return 0;
36
37}
38
Wolfgang Denk53677ef2008-05-20 16:00:29 +020039#if 0 /* NOT USED */
wdenkc6097192002-11-03 00:24:07 +000040int checkflash (void)
41{
42 /* TODO: XXX XXX XXX */
43 printf ("## Test not implemented yet ##\n");
44
45 return (0);
46}
47#endif
48
Becky Bruce9973e3c2008-06-09 16:03:40 -050049phys_size_t initdram (int board_type)
wdenkc6097192002-11-03 00:24:07 +000050{
wdenkc83bf6a2004-01-06 22:38:14 +000051 long size;
52 long new_bank0_end;
53 long mear1;
54 long emear1;
wdenkc6097192002-11-03 00:24:07 +000055
wdenkc83bf6a2004-01-06 22:38:14 +000056 size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
wdenkc6097192002-11-03 00:24:07 +000057
wdenkc83bf6a2004-01-06 22:38:14 +000058 new_bank0_end = size - 1;
59 mear1 = mpc824x_mpc107_getreg(MEAR1);
60 emear1 = mpc824x_mpc107_getreg(EMEAR1);
61 mear1 = (mear1 & 0xFFFFFF00) |
62 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
63 emear1 = (emear1 & 0xFFFFFF00) |
64 ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
65 mpc824x_mpc107_setreg(MEAR1, mear1);
66 mpc824x_mpc107_setreg(EMEAR1, emear1);
wdenkc6097192002-11-03 00:24:07 +000067
wdenkc83bf6a2004-01-06 22:38:14 +000068 return (size);
wdenkc6097192002-11-03 00:24:07 +000069}
70
71/*
72 * Initialize PCI Devices
73 */
74#ifndef CONFIG_PCI_PNP
75static struct pci_config_table pci_sandpoint_config_table[] = {
76#if 0
77 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
78 0x0, 0x0, 0x0, /* unknown eth0 divice */
79 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
80 PCI_ENET0_MEMADDR,
81 PCI_COMMAND_IO |
82 PCI_COMMAND_MEMORY |
83 PCI_COMMAND_MASTER }},
84 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
85 0x0, 0x0, 0x0, /* unknown eth1 device */
86 pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
87 PCI_ENET1_MEMADDR,
88 PCI_COMMAND_IO |
89 PCI_COMMAND_MEMORY |
90 PCI_COMMAND_MASTER }},
91#endif
92 { }
93};
94#endif
95
96struct pci_controller hose = {
97#ifndef CONFIG_PCI_PNP
98 config_table: pci_sandpoint_config_table,
99#endif
100};
101
stroesead10dd92003-02-14 11:21:23 +0000102void pci_init_board(void)
wdenkc6097192002-11-03 00:24:07 +0000103{
104 pci_mpc824x_init(&hose);
105}
Ben Warren8ca0b3f2008-08-31 10:45:44 -0700106
107int board_eth_init(bd_t *bis)
108{
109 return pci_eth_init(bis);
110}