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Julien May5c374c92008-06-23 13:57:52 +02001/*
2 * Copyright (C) 2008 Miromico AG
3 *
4 * Mostly copied form atmel ATNGW100 sources
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Julien May5c374c92008-06-23 13:57:52 +02007 */
8
Julien May5c374c92008-06-23 13:57:52 +02009#include <common.h>
Ben Warren89973f82008-08-31 22:22:04 -070010#include <netdev.h>
Julien May5c374c92008-06-23 13:57:52 +020011
12#include <asm/io.h>
13#include <asm/sdram.h>
14#include <asm/arch/clk.h>
Julien May5c374c92008-06-23 13:57:52 +020015#include <asm/arch/hmatrix.h>
Andreas Bießmann5d73bc72010-11-04 23:15:30 +000016#include <asm/arch/hardware.h>
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070017#include <asm/arch/mmu.h>
Haavard Skinnemoenab0df362008-08-29 21:09:49 +020018#include <asm/arch/portmux.h>
Julien May5c374c92008-06-23 13:57:52 +020019
20DECLARE_GLOBAL_DATA_PTR;
21
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070022struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
23 {
Andreas Bießmanne9ed41c2015-02-06 23:06:42 +010024 .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
25 .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
26 .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070027 | MMU_VMR_CACHE_NONE,
28 }, {
Andreas Bießmanne9ed41c2015-02-06 23:06:42 +010029 .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
30 .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
31 .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070032 | MMU_VMR_CACHE_WRBACK,
33 },
34};
35
Julien May5c374c92008-06-23 13:57:52 +020036static const struct sdram_config sdram_config = {
37 .data_bits = SDRAM_DATA_32BIT,
38 .row_bits = 13,
39 .col_bits = 9,
40 .bank_bits = 2,
41 .cas = 3,
42 .twr = 2,
43 .trc = 7,
44 .trp = 2,
45 .trcd = 2,
46 .tras = 5,
47 .txsr = 5,
48 /* 7.81 us */
49 .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
50};
51
Julien May5c374c92008-06-23 13:57:52 +020052#ifdef CONFIG_CMD_NET
53int board_eth_init(bd_t *bis)
54{
Andreas Bießmannf4278b72010-11-04 23:15:31 +000055 return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
56 bis->bi_phy_id[0]);
Julien May5c374c92008-06-23 13:57:52 +020057}
58#endif
59
60int board_early_init_f(void)
61{
62 /* Enable SDRAM in the EBI mux */
63 hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
64
Haavard Skinnemoenab0df362008-08-29 21:09:49 +020065 portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
Andreas Bießmann18667862015-02-06 23:06:43 +010066 sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
67
Haavard Skinnemoenab0df362008-08-29 21:09:49 +020068 portmux_enable_usart1(PORTMUX_DRIVE_MIN);
Julien May5c374c92008-06-23 13:57:52 +020069
70#if defined(CONFIG_MACB)
Haavard Skinnemoenab0df362008-08-29 21:09:49 +020071 portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
Julien May5c374c92008-06-23 13:57:52 +020072#endif
73#if defined(CONFIG_MMC)
Haavard Skinnemoenab0df362008-08-29 21:09:49 +020074 portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
Julien May5c374c92008-06-23 13:57:52 +020075#endif
76 return 0;
77}
78
Haavard Skinnemoen25e68542008-08-31 18:46:35 +020079int board_early_init_r(void)
Julien May5c374c92008-06-23 13:57:52 +020080{
81 gd->bd->bi_phy_id[0] = 0x01;
Haavard Skinnemoen25e68542008-08-31 18:46:35 +020082 return 0;
Julien May5c374c92008-06-23 13:57:52 +020083}
84
Haavard Skinnemoen36d375f2008-08-31 18:24:24 +020085int board_postclk_init(void)
Julien May5c374c92008-06-23 13:57:52 +020086{
87 /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
Haavard Skinnemoenabdde2b2008-08-31 18:07:35 +020088 gclk_enable_output(3, PORTMUX_DRIVE_LOW);
89 gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
Haavard Skinnemoen36d375f2008-08-31 18:24:24 +020090 return 0;
Julien May5c374c92008-06-23 13:57:52 +020091}