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Wolfgang Denkac7eb8a32005-09-14 23:53:32 +02001/*
2 * Board specific setup info
3 *
4 * (C) Copyright 2004 Ales Jindra <jindra@2n.cz>
5 * (C) Copyright 2005 Ladislav Michl <michl@2n.cz>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <config.h>
27#include <version.h>
28
29_TEXT_BASE:
Wolfgang Denk14d0a022010-10-07 21:51:12 +020030 .word CONFIG_SYS_TEXT_BASE /* SDRAM load addr from config.mk */
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +020031
32OMAP5910_LPG1_BASE: .word 0xfffbd000
33OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800
34OMAP5910_MPU_TC_BASE: .word 0xfffecc00
35OMAP5910_MPU_CLKM_BASE: .word 0xfffece00
36OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800
37OMAP5910_DPLL1_BASE: .word 0xfffecf00
38OMAP5910_GPIO_BASE: .word 0xfffce000
39OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800
40OMAP5910_MPUI_BASE: .word 0xfffec900
41
42_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL
43_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK
44
45OMAP5910_MPUI_CTRL: .word 0x0000ff1b
46
47VAL_EMIFS_CS0_CONFIG: .word 0x00009090
48VAL_EMIFS_CS1_CONFIG: .word 0x00003031
49VAL_EMIFS_CS2_CONFIG: .word 0x0000a0a1
50VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0
51VAL_EMIFS_DYN_WAIT: .word 0x00000000
52/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */
53 /* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */
54
55#if (PHYS_SDRAM_1_SIZE == SZ_32M)
56VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
57#else
58VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
59#endif
60
Wolfgang Denkb9365a22006-07-21 11:56:05 +020061VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +020062VAL_EMIFF_MRS: .word 0x00000037
63
Wolfgang Denkb9365a22006-07-21 11:56:05 +020064/*
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +020065 * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator)
66 * GPIO07 - LAN91C111 reset
67 */
68GPIO_DIRECTION:
69 .word 0x0000ff6f
70/*
71 * Disable everything (green LED is connected via invertor)
72 */
73GPIO_OUTPUT:
74 .word 0x00000010
75
76MUX_CONFIG_BASE:
77 .word 0xfffe1000
78
79MUX_CONFIG_VALUES:
80 .align 4
81 .word 0x00000000 @ FUNC_MUX_CTRL_0
82 .word 0x00000000 @ FUNC_MUX_CTRL_1
83 .word 0x00000000 @ FUNC_MUX_CTRL_2
84 .word 0x00000000 @ FUNC_MUX_CTRL_3
85 .word 0x00000000 @ FUNC_MUX_CTRL_4
86 .word 0x02080480 @ FUNC_MUX_CTRL_5
87 .word 0x0100001c @ FUNC_MUX_CTRL_6
88 .word 0x0004800b @ FUNC_MUX_CTRL_7
89 .word 0x10001200 @ FUNC_MUX_CTRL_8
90 .word 0x01201012 @ FUNC_MUX_CTRL_9
91 .word 0x02082248 @ FUNC_MUX_CTRL_A
92 .word 0x00000248 @ FUNC_MUX_CTRL_B
93 .word 0x12240000 @ FUNC_MUX_CTRL_C
94 .word 0x00002000 @ FUNC_MUX_CTRL_D
95 .word 0x00000000 @ PULL_DWN_CTRL_0
96 .word 0x00000800 @ PULL_DWN_CTRL_1
97 .word 0x01801000 @ PULL_DWN_CTRL_2
98 .word 0x00000000 @ PULL_DWN_CTRL_3
99 .word 0x00000000 @ GATE_INH_CTRL_0
100 .word 0x00000000 @ VOLTAGE_CTRL_0
101 .word 0x00000000 @ TEST_DBG_CTRL_0
102 .word 0x00000006 @ MOD_CONF_CTRL_0
103 .word 0x0000eaef @ COMP_MODE_CTRL_0
104
105MUX_CONFIG_OFFSETS:
106 .align 1
107 .byte 0x00 @ FUNC_MUX_CTRL_0
108 .byte 0x04 @ FUNC_MUX_CTRL_1
Wolfgang Denkb9365a22006-07-21 11:56:05 +0200109 .byte 0x08 @ FUNC_MUX_CTRL_2
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +0200110 .byte 0x10 @ FUNC_MUX_CTRL_3
111 .byte 0x14 @ FUNC_MUX_CTRL_4
112 .byte 0x18 @ FUNC_MUX_CTRL_5
113 .byte 0x1c @ FUNC_MUX_CTRL_6
114 .byte 0x20 @ FUNC_MUX_CTRL_7
115 .byte 0x24 @ FUNC_MUX_CTRL_8
116 .byte 0x28 @ FUNC_MUX_CTRL_9
117 .byte 0x2c @ FUNC_MUX_CTRL_A
118 .byte 0x30 @ FUNC_MUX_CTRL_B
119 .byte 0x34 @ FUNC_MUX_CTRL_C
120 .byte 0x38 @ FUNC_MUX_CTRL_D
121 .byte 0x40 @ PULL_DWN_CTRL_0
122 .byte 0x44 @ PULL_DWN_CTRL_1
123 .byte 0x48 @ PULL_DWN_CTRL_2
124 .byte 0x4c @ PULL_DWN_CTRL_3
125 .byte 0x50 @ GATE_INH_CTRL_0
126 .byte 0x60 @ VOLTAGE_CTRL_0
127 .byte 0x70 @ TEST_DBG_CTRL_0
128 .byte 0x80 @ MOD_CONF_CTRL_0
129 .byte 0x0c @ COMP_MODE_CTRL_0
130 .byte 0xff
131
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100132.globl lowlevel_init
133lowlevel_init:
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +0200134 /* Improve performance a bit... */
135 mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
136 mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
137 mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
138 orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
139 mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
140 mov r1, #0x00
141 mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
142 nop
143 nop
144 nop
145 nop
146
147 /* Setup clocking mode */
Wolfgang Denk87a5c732006-07-21 11:38:33 +0200148 ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
149 ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +0200150 bic r1, r1, #(7 << 11) @ clear clock select
151 orr r1, r1, #(2 << 11) @ set synchronous scalable
Wolfgang Denk87a5c732006-07-21 11:38:33 +0200152 mov r2, #0
153loop:
154 cmp r2, #1 @ this loop will wait for at least 100 cycles
155 streqh r1, [r0, #0x18] @ before issuing next request from MPU
156 add r2, r2, #1 @ on the 1st run code is loaded into I-cache
157 cmp r2, #16 @ and second run will set clocking mode
158 bne loop
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +0200159 nop
160
Wolfgang Denk87a5c732006-07-21 11:38:33 +0200161 /* Setup clock dividers */
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +0200162 ldr r1, _OMAP5910_ARM_CKCTL
163 orr r1, r1, #0x2000 @ enable DSP clock
Wolfgang Denk87a5c732006-07-21 11:38:33 +0200164 strh r1, [r0] @ setup clock divisors
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +0200165
166 /* Setup DPLL to generate requested freq */
167 ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register
168 mov r1, #0x0010 @ set PLL_ENABLE
169 orr r1, r1, #0x2000 @ set IOB to new locking
170 orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
171 orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
172 strh r1, [r0] @ write
173
174locking:
175 ldrh r1, [r0] @ get DPLL value
176 tst r1, #0x01
177 beq locking @ while LOCK not set
178
179 /* Enable clock */
180 ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
181 mov r1, #(1 << 10) @ disable idle mode do not check
182 @ nWAKEUP pin, other remain active
Wolfgang Denkb9365a22006-07-21 11:56:05 +0200183 strh r1, [r0, #0x04]
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +0200184 ldr r1, _OMAP5910_ARM_EN_CLK
185 strh r1, [r0, #0x08]
186 mov r1, #0x003f @ FLASH.RP not enabled in idle and
Wolfgang Denk87a5c732006-07-21 11:38:33 +0200187 strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +0200188
189 /* Configure 5910 pins functions to match our board. */
190 ldr r0, MUX_CONFIG_BASE
191 adr r1, MUX_CONFIG_VALUES
192 adr r2, MUX_CONFIG_OFFSETS
Wolfgang Denkb9365a22006-07-21 11:56:05 +0200193next_mux_cfg:
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +0200194 ldrb r3, [r2], #1
195 ldr r4, [r1], #4
196 cmp r3, #0xff
197 strne r4, [r0, r3]
198 bne next_mux_cfg
199
200 /* Configure GPIO pins (also disables Green LED) */
201 ldr r0, OMAP5910_GPIO_BASE
202 ldr r1, GPIO_OUTPUT
203 strh r1, [r0, #0x04]
204 ldr r1, GPIO_DIRECTION
205 strh r1, [r0, #0x08]
206
207 /* EnablePeripherals */
208 ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit
209 mov r1, #0x0001 @ Peripheral enable
210 strh r1, [r0, #0x14]
211
212 /* Program LED Pulse Generator */
213 ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator
214 mov r1, #0x7F @ Set obscure frequency in
215 strb r1, [r0, #0x00] @ LCR
216 mov r1, #0x01 @ Enable clock (CLK_EN) in
217 strb r1, [r0, #0x04] @ PMR
218
219 /* TIPB Lock UART1 */
220 ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches
221 mov r1, #1 @ ARM allocated
222 strh r1, [r0,#0x04] @ clear IRQ line and status bits
223 strh r1, [r0,#0x00]
224 ldrh r1, [r0,#0x04]
225
226 /* Disable watchdog */
227 ldr r0, OMAP5910_MPU_WD_TIMER_BASE
228 mov r1, #0xf5
229 strh r1, [r0, #0x8]
230 mov r1, #0xa0
231 strh r1, [r0, #0x8]
232
233 /* Enable MCLK */
234 ldr r0, OMAP5910_ULPD_PWR_MNG_BASE
235 mov r1, #0x6
236 strh r1, [r0, #0x34]
237 strh r1, [r0, #0x34]
238
239 /* Setup clock divisors */
Wolfgang Denkb9365a22006-07-21 11:56:05 +0200240 ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +0200241
242 mov r1, #0x0010 @ set PLL_ENABLE
Wolfgang Denkb9365a22006-07-21 11:56:05 +0200243 orr r1, r1, #0x2000 @ set IOB to new locking
244 strh r1, [r0] @ write
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +0200245
246ulocking:
247 ldrh r1, [r0] @ get DPLL value
Wolfgang Denkb9365a22006-07-21 11:56:05 +0200248 tst r1, #1
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +0200249 beq ulocking @ while LOCK not set
250
251 /* EMIF init */
252 ldr r0, OMAP5910_MPU_TC_BASE
253 ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG
254 bic r1, r1, #0x0c @ pwr down disabled, flash WP
255 orr r1, r1, #0x01
256 str r1, [r0, #0x0c]
Wolfgang Denkb9365a22006-07-21 11:56:05 +0200257
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +0200258 ldr r1, VAL_EMIFS_CS0_CONFIG
259 str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG
260 ldr r1, VAL_EMIFS_CS1_CONFIG
261 str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG
262 ldr r1, VAL_EMIFS_CS2_CONFIG
263 str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG
264 ldr r1, VAL_EMIFS_CS3_CONFIG
265 str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG
266 ldr r1, VAL_EMIFS_DYN_WAIT
267 str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT
268
269 /* Setup SDRAM */
270 ldr r1, VAL_EMIFF_SDRAM_CONFIG
271 str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG
272 ldr r1, VAL_EMIFF_SDRAM_CONFIG2
273 str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2
274 ldr r1, VAL_EMIFF_MRS
275 str r1, [r0, #0x24] @ EMIFF_MRS
276 /* SDRAM needs 100us to stabilize */
277 mov r0, #0x4000
278sdelay:
279 subs r0, r0, #0x1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200280 bne sdelay
Wolfgang Denkac7eb8a32005-09-14 23:53:32 +0200281
282 /* back to arch calling code */
283 mov pc, lr
284.end