| Eric Nelson | 6904172 | 2013-02-19 10:07:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Boundary Devices Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | |
| 14 | * You should have received a copy of the GNU General Public License along |
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
| 17 | */ |
| 18 | #ifndef __ASM_ARCH_MX6Q_DDR_H__ |
| 19 | #define __ASM_ARCH_MX6Q_DDR_H__ |
| 20 | |
| 21 | #ifndef CONFIG_MX6Q |
| 22 | #error "wrong CPU" |
| 23 | #endif |
| 24 | |
| 25 | #define MX6_IOM_DRAM_DQM0 0x020e05ac |
| 26 | #define MX6_IOM_DRAM_DQM1 0x020e05b4 |
| 27 | #define MX6_IOM_DRAM_DQM2 0x020e0528 |
| 28 | #define MX6_IOM_DRAM_DQM3 0x020e0520 |
| 29 | #define MX6_IOM_DRAM_DQM4 0x020e0514 |
| 30 | #define MX6_IOM_DRAM_DQM5 0x020e0510 |
| 31 | #define MX6_IOM_DRAM_DQM6 0x020e05bc |
| 32 | #define MX6_IOM_DRAM_DQM7 0x020e05c4 |
| 33 | |
| 34 | #define MX6_IOM_DRAM_CAS 0x020e056c |
| 35 | #define MX6_IOM_DRAM_RAS 0x020e0578 |
| 36 | #define MX6_IOM_DRAM_RESET 0x020e057c |
| 37 | #define MX6_IOM_DRAM_SDCLK_0 0x020e0588 |
| 38 | #define MX6_IOM_DRAM_SDCLK_1 0x020e0594 |
| 39 | #define MX6_IOM_DRAM_SDBA2 0x020e058c |
| 40 | #define MX6_IOM_DRAM_SDCKE0 0x020e0590 |
| 41 | #define MX6_IOM_DRAM_SDCKE1 0x020e0598 |
| 42 | #define MX6_IOM_DRAM_SDODT0 0x020e059c |
| 43 | #define MX6_IOM_DRAM_SDODT1 0x020e05a0 |
| 44 | |
| 45 | #define MX6_IOM_DRAM_SDQS0 0x020e05a8 |
| 46 | #define MX6_IOM_DRAM_SDQS1 0x020e05b0 |
| 47 | #define MX6_IOM_DRAM_SDQS2 0x020e0524 |
| 48 | #define MX6_IOM_DRAM_SDQS3 0x020e051c |
| 49 | #define MX6_IOM_DRAM_SDQS4 0x020e0518 |
| 50 | #define MX6_IOM_DRAM_SDQS5 0x020e050c |
| 51 | #define MX6_IOM_DRAM_SDQS6 0x020e05b8 |
| 52 | #define MX6_IOM_DRAM_SDQS7 0x020e05c0 |
| 53 | |
| 54 | #define MX6_IOM_GRP_B0DS 0x020e0784 |
| 55 | #define MX6_IOM_GRP_B1DS 0x020e0788 |
| 56 | #define MX6_IOM_GRP_B2DS 0x020e0794 |
| 57 | #define MX6_IOM_GRP_B3DS 0x020e079c |
| 58 | #define MX6_IOM_GRP_B4DS 0x020e07a0 |
| 59 | #define MX6_IOM_GRP_B5DS 0x020e07a4 |
| 60 | #define MX6_IOM_GRP_B6DS 0x020e07a8 |
| 61 | #define MX6_IOM_GRP_B7DS 0x020e0748 |
| 62 | #define MX6_IOM_GRP_ADDDS 0x020e074c |
| 63 | #define MX6_IOM_DDRMODE_CTL 0x020e0750 |
| 64 | #define MX6_IOM_GRP_DDRPKE 0x020e0758 |
| 65 | #define MX6_IOM_GRP_DDRMODE 0x020e0774 |
| 66 | #define MX6_IOM_GRP_CTLDS 0x020e078c |
| 67 | #define MX6_IOM_GRP_DDR_TYPE 0x020e0798 |
| 68 | |
| 69 | #endif /*__ASM_ARCH_MX6Q_DDR_H__ */ |