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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* sdram_init.c - automatic memory sizing */
25
26#include <common.h>
27#include <74xx_7xx.h>
28#include <galileo/memory.h>
29#include <galileo/pci.h>
30#include <galileo/gt64260R.h>
31#include <net.h>
32
33#include "eth.h"
34#include "mpsc.h"
35#include "i2c.h"
36#include "64260.h"
37
38/* #define DEBUG */
39#define MAP_PCI
40
41#ifdef DEBUG
42#define DP(x) x
43#else
44#define DP(x)
45#endif
46
47#define GB (1 << 30)
48
49/* structure to store the relevant information about an sdram bank */
50typedef struct sdram_info {
51 uchar drb_size;
52 uchar registered, ecc;
53 uchar tpar;
54 uchar tras_clocks;
55 uchar burst_len;
56 uchar banks, slot;
57 int size; /* detected size, not from I2C but from dram_size() */
58} sdram_info_t;
59
60#ifdef DEBUG
61void dump_dimm_info(struct sdram_info *d)
62{
63 static const char *ecc_legend[]={""," Parity"," ECC"};
64 printf("dimm%s %sDRAM: %dMibytes:\n",
65 ecc_legend[d->ecc],
66 d->registered?"R":"",
67 (d->size>>20));
68 printf(" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
69 d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
70 d->banks, d->slot);
71}
72#endif
73
74static int
75memory_map_bank(unsigned int bankNo,
76 unsigned int bankBase,
77 unsigned int bankLength)
78{
79#ifdef DEBUG
80 if (bankLength > 0) {
81 printf("mapping bank %d at %08x - %08x\n",
82 bankNo, bankBase, bankBase + bankLength - 1);
83 } else {
84 printf("unmapping bank %d\n", bankNo);
85 }
86#endif
87
88 memoryMapBank(bankNo, bankBase, bankLength);
89
90 return 0;
91}
92
93#ifdef MAP_PCI
94static int
95memory_map_bank_pci(unsigned int bankNo,
96 unsigned int bankBase,
97 unsigned int bankLength)
98{
99 PCI_HOST host;
100 for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
101 const int features=
102 PREFETCH_ENABLE |
103 DELAYED_READ_ENABLE |
104 AGGRESSIVE_PREFETCH |
105 READ_LINE_AGGRESSIVE_PREFETCH |
106 READ_MULTI_AGGRESSIVE_PREFETCH |
107 MAX_BURST_4 |
108 PCI_NO_SWAP;
109
110 pciMapMemoryBank(host, bankNo, bankBase, bankLength);
111
112 pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
113 bankLength);
114
115 pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
116 }
117 return 0;
118}
119#endif
120
121/* ------------------------------------------------------------------------- */
122
123/* much of this code is based on (or is) the code in the pip405 port */
124/* thanks go to the authors of said port - Josh */
125
126
127/*
128 * translate ns.ns/10 coding of SPD timing values
129 * into 10 ps unit values
130 */
131static inline unsigned short
132NS10to10PS(unsigned char spd_byte)
133{
134 unsigned short ns, ns10;
135
136 /* isolate upper nibble */
137 ns = (spd_byte >> 4) & 0x0F;
138 /* isolate lower nibble */
139 ns10 = (spd_byte & 0x0F);
140
141 return(ns*100 + ns10*10);
142}
143
144/*
145 * translate ns coding of SPD timing values
146 * into 10 ps unit values
147 */
148static inline unsigned short
149NSto10PS(unsigned char spd_byte)
150{
151 return(spd_byte*100);
152}
153
154#ifdef CONFIG_ZUMA_V2
155static int
156check_dimm(uchar slot, sdram_info_t *info)
157{
wdenk8bde7f72003-06-27 21:31:46 +0000158 /* assume 2 dimms, 2 banks each 256M - we dont have an
wdenkc6097192002-11-03 00:24:07 +0000159 * dimm i2c so rely on the detection routines later */
160
161 memset(info, 0, sizeof(*info));
162
163 info->slot = slot;
164 info->banks = 2; /* Detect later */
165 info->registered = 0;
166 info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit
167 but doesn't matter, both do same
168 thing in setup_sdram() */
169 info->tpar = 3;
170 info->tras_clocks = 5;
171 info->burst_len = 4;
172#ifdef CONFIG_ECC
173 info->ecc = 0; /* Detect later */
174#endif /* CONFIG_ECC */
175 return 0;
176}
177
178#else /* ! CONFIG_ZUMA_V2 */
179
180/* This code reads the SPD chip on the sdram and populates
181 * the array which is passed in with the relevant information */
182static int
183check_dimm(uchar slot, sdram_info_t *info)
184{
185 DECLARE_GLOBAL_DATA_PTR;
186 uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
187 int ret;
188 uchar rows, cols, sdram_banks, supp_cal, width, cal_val;
189 ulong tmemclk;
190 uchar trp_clocks, trcd_clocks;
191 uchar data[128];
192
193 get_clocks ();
194
wdenk8bde7f72003-06-27 21:31:46 +0000195 tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */
wdenkc6097192002-11-03 00:24:07 +0000196
197#ifdef CONFIG_EVB64260_750CX
198 if (0 != slot) {
199 printf("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
200 printf(" called with slot=%d insetad!\n", slot);
201 return 0;
202 }
203#endif
204 DP(puts("before i2c read\n"));
205
206 ret = i2c_read(addr, 0, 128, data, 0);
207
208 DP(puts("after i2c read\n"));
209
210 /* zero all the values */
211 memset(info, 0, sizeof(*info));
212
213 if (ret) {
214 DP(printf("No DIMM in slot %d [err = %x]\n", slot, ret));
215 return 0;
216 }
217
218 /* first, do some sanity checks */
219 if (data[2] != 0x4) {
220 printf("Not SDRAM in slot %d\n", slot);
221 return 0;
222 }
223
224 /* get various information */
225 rows = data[3];
226 cols = data[4];
227 info->banks = data[5];
228 sdram_banks = data[17];
229 width = data[13] & 0x7f;
230
231 DP(printf("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
232
233 /* check if the memory is registered */
234 if (data[21] & (BIT1 | BIT4))
235 info->registered = 1;
236
237#ifdef CONFIG_ECC
238 /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
239 info->ecc = (data[11] & 2) >> 1;
240#endif
241
242 /* bit 1 is CL2, bit 2 is CL3 */
243 supp_cal = (data[18] & 0x6) >> 1;
244
245 /* compute the relevant clock values */
246 trp_clocks = (NSto10PS(data[27])+(tmemclk-1)) / tmemclk;
247 trcd_clocks = (NSto10PS(data[29])+(tmemclk-1)) / tmemclk;
248 info->tras_clocks = (NSto10PS(data[30])+(tmemclk-1)) / tmemclk;
249
250 DP(printf("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
251 trp_clocks, trcd_clocks, info->tras_clocks));
252
253 /* try a CAS latency of 3 first... */
254 cal_val = 0;
255 if (supp_cal & 3) {
256 if (NS10to10PS(data[9]) <= tmemclk)
257 cal_val = 3;
258 }
259
260 /* then 2... */
261 if (supp_cal & 2) {
262 if (NS10to10PS(data[23]) <= tmemclk)
263 cal_val = 2;
264 }
265
266 DP(printf("cal_val = %d\n", cal_val));
267
268 /* bummer, did't work... */
269 if (cal_val == 0) {
270 DP(printf("Couldn't find a good CAS latency\n"));
271 return 0;
272 }
273
274 /* get the largest delay -- these values need to all be the same
275 * see Res#6 */
276 info->tpar = cal_val;
277 if (trp_clocks > info->tpar)
278 info->tpar = trp_clocks;
279 if (trcd_clocks > info->tpar)
280 info->tpar = trcd_clocks;
281
282 DP(printf("tpar set to: %d\n", info->tpar));
283
284#ifdef CFG_BROKEN_CL2
285 if (info->tpar == 2){
286 info->tpar = 3;
wdenk8bde7f72003-06-27 21:31:46 +0000287 DP(printf("tpar fixed-up to: %d\n", info->tpar));
wdenkc6097192002-11-03 00:24:07 +0000288 }
289#endif
290 /* compute the module DRB size */
291 info->drb_size = (((1 << (rows + cols)) * sdram_banks) * width) / _16M;
292
293 DP(printf("drb_size set to: %d\n", info->drb_size));
294
295 /* find the burst len */
296 info->burst_len = data[16] & 0xf;
297 if ((info->burst_len & 8) == 8) {
298 info->burst_len = 1;
299 } else if ((info->burst_len & 4) == 4) {
300 info->burst_len = 0;
301 } else {
302 return 0;
303 }
304
305 info->slot = slot;
306 return 0;
307}
308#endif /* ! CONFIG_ZUMA_V2 */
309
310static int
311setup_sdram_common(sdram_info_t info[2])
312{
wdenk8bde7f72003-06-27 21:31:46 +0000313 ulong tmp;
wdenkc6097192002-11-03 00:24:07 +0000314 int tpar=2, tras_clocks=5, registered=1, ecc=2;
315
316 if(!info[0].banks && !info[1].banks) return 0;
317
318 if(info[0].banks) {
319 if(info[0].tpar>tpar) tpar=info[0].tpar;
320 if(info[0].tras_clocks>tras_clocks) tras_clocks=info[0].tras_clocks;
321 if(!info[0].registered) registered=0;
322 if(info[0].ecc!=2) ecc=0;
323 }
324
325 if(info[1].banks) {
326 if(info[1].tpar>tpar) tpar=info[1].tpar;
327 if(info[1].tras_clocks>tras_clocks) tras_clocks=info[1].tras_clocks;
328 if(!info[1].registered) registered=0;
329 if(info[1].ecc!=2) ecc=0;
330 }
331
332 /* SDRAM configuration */
333 tmp = GTREGREAD(SDRAM_CONFIGURATION);
334
335 /* Turn on physical interleave if both DIMMs
336 * have even numbers of banks. */
337 if( (info[0].banks == 0 || info[0].banks == 2) &&
338 (info[1].banks == 0 || info[1].banks == 2) ) {
339 /* physical interleave on */
340 tmp &= ~(1 << 15);
341 } else {
342 /* physical interleave off */
343 tmp |= (1 << 15);
344 }
345
346 tmp |= (registered << 17);
347
348 /* Use buffer 1 to return read data to the CPU
349 * See Res #12 */
350 tmp |= (1 << 26);
351
352 GT_REG_WRITE(SDRAM_CONFIGURATION, tmp);
353 DP(printf("SDRAM config: %08x\n",
354 GTREGREAD(SDRAM_CONFIGURATION)));
355
356 /* SDRAM timing */
357 tmp = (((tpar == 3) ? 2 : 1) |
358 (((tpar == 3) ? 2 : 1) << 2) |
359 (((tpar == 3) ? 2 : 1) << 4) |
360 (tras_clocks << 8));
361
362#ifdef CONFIG_ECC
363 /* Setup ECC */
364 if (ecc == 2) tmp |= 1<<13;
365#endif /* CONFIG_ECC */
366
367 GT_REG_WRITE(SDRAM_TIMING, tmp);
368 DP(printf("SDRAM timing: %08x (%d,%d,%d,%d)\n",
369 GTREGREAD(SDRAM_TIMING), tpar,tpar,tpar,tras_clocks));
370
371 /* SDRAM address decode register */
372 /* program this with the default value */
373 GT_REG_WRITE(SDRAM_ADDRESS_DECODE, 0x2);
374 DP(printf("SDRAM decode: %08x\n",
375 GTREGREAD(SDRAM_ADDRESS_DECODE)));
376
377 return 0;
378}
379
380/* sets up the GT properly with information passed in */
381static int
382setup_sdram(sdram_info_t *info)
383{
384 ulong tmp, check;
385 ulong *addr = 0;
386 int i;
387
388 /* sanity checking */
389 if (! info->banks) return 0;
390
391 /* ---------------------------- */
392 /* Program the GT with the discovered data */
393
394 /* bank parameters */
395 tmp = (0xf<<16); /* leave all virt bank pages open */
396
397 DP(printf("drb_size: %d\n", info->drb_size));
398 switch (info->drb_size) {
399 case 1:
400 tmp |= (1 << 14);
401 break;
402 case 4:
403 case 8:
404 tmp |= (2 << 14);
405 break;
406 case 16:
407 case 32:
408 tmp |= (3 << 14);
409 break;
410 default:
411 printf("Error in dram size calculation\n");
412 return 1;
413 }
414
415 /* SDRAM bank parameters */
416 /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
417 GT_REG_WRITE(SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
418 GT_REG_WRITE(SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
419 DP(printf("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot, info->slot*2, (info->slot*2)+1, tmp));
420
421 /* set the SDRAM configuration for each bank */
422 for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
423 DP(printf("*** Running a MRS cycle for bank %d ***\n", i));
424
425 /* map the bank */
426 memory_map_bank(i, 0, GB/4);
427
428 /* set SDRAM mode */
429 GT_REG_WRITE(SDRAM_OPERATION_MODE, 0x3);
430 check = GTREGREAD(SDRAM_OPERATION_MODE);
431
432 /* dummy write */
433 *addr = 0;
434
435 /* wait for the command to complete */
436 while ((GTREGREAD(SDRAM_OPERATION_MODE) & (1 << 31)) == 0)
437 ;
438
439 /* switch back to normal operation mode */
440 GT_REG_WRITE(SDRAM_OPERATION_MODE, 0);
441 check = GTREGREAD(SDRAM_OPERATION_MODE);
442
443 /* unmap the bank */
444 memory_map_bank(i, 0, 0);
445 DP(printf("*** MRS cycle for bank %d done ***\n", i));
446 }
447
448 return 0;
449}
450
451/*
452 * Check memory range for valid RAM. A simple memory test determines
453 * the actually available RAM size between addresses `base' and
454 * `base + maxsize'. Some (not all) hardware errors are detected:
455 * - short between address lines
456 * - short between data lines
457 */
458static long int
459dram_size(long int *base, long int maxsize)
460{
461 volatile long int *addr, *b=base;
462 long int cnt, val, save1, save2;
463
464#define STARTVAL (1<<20) /* start test at 1M */
465 for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
466 addr = base + cnt; /* pointer arith! */
467
468 save1=*addr; /* save contents of addr */
469 save2=*b; /* save contents of base */
470
471 *addr=cnt; /* write cnt to addr */
472 *b=0; /* put null at base */
473
474 /* check at base address */
475 if ((*b) != 0) {
476 *addr=save1; /* restore *addr */
477 *b=save2; /* restore *b */
478 return (0);
479 }
480 val = *addr; /* read *addr */
481
482 *addr=save1;
483 *b=save2;
484
485 if (val != cnt) {
486 /* fix boundary condition.. STARTVAL means zero */
487 if(cnt==STARTVAL/sizeof(long)) cnt=0;
488 return (cnt * sizeof(long));
489 }
490 }
491 return maxsize;
492}
493
494/* ------------------------------------------------------------------------- */
495
496/* U-Boot interface function to SDRAM init - this is where all the
497 * controlling logic happens */
498long int
499initdram(int board_type)
500{
501 ulong checkbank[4] = { [0 ... 3] = 0 };
502 int bank_no;
wdenk8bde7f72003-06-27 21:31:46 +0000503 ulong total;
wdenkc6097192002-11-03 00:24:07 +0000504 int nhr;
505 sdram_info_t dimm_info[2];
506
507
508 /* first, use the SPD to get info about the SDRAM */
509
510 /* check the NHR bit and skip mem init if it's already done */
511 nhr = get_hid0() & (1 << 16);
512
513 if (nhr) {
514 printf("Skipping SDRAM setup due to NHR bit being set\n");
515 } else {
516 /* DIMM0 */
517 check_dimm(0, &dimm_info[0]);
518
519 /* DIMM1 */
520#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
521 check_dimm(1, &dimm_info[1]);
522#else /* CONFIG_EVB64260_750CX */
523 memset(&dimm_info[1], 0, sizeof(sdram_info_t));
524#endif
525
526 /* unmap all banks */
527 memory_map_bank(0, 0, 0);
528 memory_map_bank(1, 0, 0);
529 memory_map_bank(2, 0, 0);
530 memory_map_bank(3, 0, 0);
531
532 /* Now, program the GT with the correct values */
533 if (setup_sdram_common(dimm_info)) {
534 printf("Setup common failed.\n");
535 }
536
537 if (setup_sdram(&dimm_info[0])) {
538 printf("Setup for DIMM1 failed.\n");
539 }
540
541 if (setup_sdram(&dimm_info[1])) {
542 printf("Setup for DIMM2 failed.\n");
543 }
544
545 /* set the NHR bit */
546 set_hid0(get_hid0() | (1 << 16));
547 }
548 /* next, size the SDRAM banks */
549
550 total = 0;
551 if (dimm_info[0].banks > 0) checkbank[0] = 1;
552 if (dimm_info[0].banks > 1) checkbank[1] = 1;
553 if (dimm_info[0].banks > 2)
554 printf("Error, SPD claims DIMM1 has >2 banks\n");
555
556 if (dimm_info[1].banks > 0) checkbank[2] = 1;
557 if (dimm_info[1].banks > 1) checkbank[3] = 1;
558 if (dimm_info[1].banks > 2)
559 printf("Error, SPD claims DIMM2 has >2 banks\n");
560
561 /* Generic dram sizer: works even if we don't have i2c DIMMs,
562 * as long as the timing settings are more or less correct */
563
564 /*
565 * pass 1: size all the banks, using first bat (0-256M)
566 * limitation: we only support 256M per bank due to
567 * us only having 1 BAT for all DRAM
568 */
569 for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
570 /* skip over banks that are not populated */
571 if (! checkbank[bank_no])
572 continue;
573
574 DP(printf("checking bank %d\n", bank_no));
575
576 memory_map_bank(bank_no, 0, GB/4);
577 checkbank[bank_no] = dram_size(NULL, GB/4);
578 memory_map_bank(bank_no, 0, 0);
579
580 DP(printf("bank %d %08lx\n", bank_no, checkbank[bank_no]));
581 }
582
583 /*
584 * pass 2: contiguously map each bank into physical address
585 * space.
586 */
587 dimm_info[0].banks=dimm_info[1].banks=0;
588 for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
589 if(!checkbank[bank_no]) continue;
590
591 dimm_info[bank_no/2].banks++;
592 dimm_info[bank_no/2].size+=checkbank[bank_no];
593
594 memory_map_bank(bank_no, total, checkbank[bank_no]);
595#ifdef MAP_PCI
596 memory_map_bank_pci(bank_no, total, checkbank[bank_no]);
597#endif
598 total += checkbank[bank_no];
599 }
600
601#ifdef CONFIG_ECC
602#ifdef CONFIG_ZUMA_V2
603 /*
604 * We always enable ECC when bank 2 and 3 are unpopulated
605 * If we 2 or 3 are populated, we CAN'T support ECC.
606 * (Zuma boards only support ECC in banks 0 and 1; assume that
607 * in that configuration, ECC chips are mounted, even for stacked
608 * chips)
609 */
610 if (checkbank[2]==0 && checkbank[3]==0) {
wdenk8bde7f72003-06-27 21:31:46 +0000611 dimm_info[0].ecc=2;
wdenkc6097192002-11-03 00:24:07 +0000612 GT_REG_WRITE(SDRAM_TIMING, GTREGREAD(SDRAM_TIMING) | (1 << 13));
613 /* TODO: do we have to run MRS cycles again? */
614 }
615#endif /* CONFIG_ZUMA_V2 */
616
617 if (GTREGREAD(SDRAM_TIMING) & (1 << 13)) {
618 puts("[ECC] ");
619 }
620#endif /* CONFIG_ECC */
621
622#ifdef DEBUG
623 dump_dimm_info(&dimm_info[0]);
624 dump_dimm_info(&dimm_info[1]);
625#endif
626 /* TODO: return at MOST 256M? */
wdenk8bde7f72003-06-27 21:31:46 +0000627 /* return total > GB/4 ? GB/4 : total; */
wdenkc6097192002-11-03 00:24:07 +0000628 return total;
629}