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gerrit.cesnet.cz / github / trini / u-boot / 8bde7f776c77b343aca29b8c7b58464d915ac245 / . / board / MAI / AmigaOneG3SE / board_asm_init.S
blob: 086b19c05240bfc1804a84461f36f4a9d596297d [file] [log] [blame]
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame^]1#include "macros.h"
wdenkc7de8292002-11-19 11:04:11 +0000[diff] [blame]2
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame^]3
4#define GLOBALINFO0 0x50
wdenkc7de8292002-11-19 11:04:11 +0000[diff] [blame]5#define GLOBALINFO0_BO (1<<7)
6#define GLOBALINFO2_B1ARBITER (1<<6)
7#define HBUSACR0 0x5c
8#define HBUSACR2_BURST (1<<0)
9#define HBUSACR2_LAT (1<<1)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame^]10
wdenkc7de8292002-11-19 11:04:11 +0000[diff] [blame]11#define RECEIVER_HOLDING 0
12#define TRANSMITTER_HOLDING 0
13#define INTERRUPT_ENABLE 1
14#define INTERRUPT_STATUS 2
15#define FIFO_CONTROL 2
16#define LINE_CONTROL 3
17#define MODEM_CONTROL 4
18#define LINE_STATUS 5
19#define MODEM_STATUS 6
20#define SCRATCH_PAD 7
21
22#define DIVISOR_LATCH_LSB 0
23#define DIVISOR_LATCH_MSB 1
24#define PRESCALER_DIVISION 5
25
26#define UART(x) (0x3f8+(x))
27
28#define GLOBALINFO0 0x50
29#define GLOBALINFO0_BO (1<<7)
30#define GLOBALINFO2_B1ARBITER (1<<6)
31#define HBUSACR0 0x5c
32#define HBUSACR2_BURST (1<<0)
33#define HBUSACR2_LAT (1<<1)
34
35#define SUPERIO_1 ((7 << 3) | (0))
36#define SUPERIO_2 ((7 << 3) | (1))
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame^]37
wdenkc7de8292002-11-19 11:04:11 +0000[diff] [blame]38 .globl board_asm_init
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame^]39
wdenkc7de8292002-11-19 11:04:11 +0000[diff] [blame]40board_asm_init:
41 mflr r29
42 /* Set 'Must-set' register */
43 li r3, 0
44 li r4, 0
45 li r5, 0x5e
46 bl pci_read_cfg_byte
47 ori r3, r3, (1<<1)
48 xori r6, r3, (1<<1)
49 li r3, 0
50 bl pci_write_cfg_byte
51
52 li r3, 0
53 li r5, 0x52
54 bl pci_read_cfg_byte
55 ori r6, r3, (1<<6)
56 li r3, 0
57 bl pci_write_cfg_byte
58
59 li r3, 0
60 li r4, 0x08
61 li r5, 0xd2
62 bl pci_read_cfg_byte
63 ori r6, r3, (1<<2)
64 li r3, 0
65 bl pci_write_cfg_byte
66
67
68 /* Do PCI reset */
69/* li r3, 0
70 li r4, 0x38
71 li r5, 0x47
72 bl pci_read_cfg_byte
73 ori r6, r3, 0x01
74 li r3, 0
75 li r4, 0x38
76 li r5, 0x47
77 bl pci_write_cfg_byte*/
78
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame^]79
wdenkc7de8292002-11-19 11:04:11 +0000[diff] [blame]80 /* Enable NVRAM for environment */
81 li r3, 0
82 li r4, 0
83 li r5, 0x56
84 li r6, 0x0B
85 bl pci_write_cfg_byte
86
87
88 /* Init Super-I/O chips */
89
90 siowb 0x40, 0x08
91 siowb 0x41, 0x01
92 siowb 0x45, 0x80
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame^]93 siowb 0x46, 0x60
wdenkc7de8292002-11-19 11:04:11 +0000[diff] [blame]94 siowb 0x47, 0x20
95 siowb 0x48, 0x01
96 siowb 0x4a, 0xc4
97 siowb 0x50, 0x0e
98 siowb 0x51, 0x76
99 siowb 0x52, 0x34
100 siowb 0x54, 0x00
101 siowb 0x55, 0x90
102 siowb 0x56, 0x99
103 siowb 0x57, 0x90
104 siowb 0x85, 0x01
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame^]105
wdenkc7de8292002-11-19 11:04:11 +0000[diff] [blame]106 /* Enable configuration mode for SuperIO */
107 li r3, 0
108 li r4, (7<<3)
109 li r5, 0x85
110 bl pci_read_cfg_byte
111 ori r6, r3, 0x02
112 mr r31, r6
113 li r3,0
114 bl pci_write_cfg_byte
115
116 /* COM1 as 3f8 */
117 outb 0x3f0, 0xe7
118 outb 0x3f1, 0xfe
119
120 /* COM2 as 2f8 */
121 outb 0x3f0, 0xe8
122 outb 0x3f1, 0xeb
123
124 /* Enable */
125 outb 0x3f0, 0xe2
126 inb r3, 0x3f1
127 ori r3, r3, 0x0c
128 outb 0x3f0, 0xe2
129 outbr 0x3f1, r3
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame^]130
wdenkc7de8292002-11-19 11:04:11 +0000[diff] [blame]131 /* Disable configuration mode */
132 li r3, 0
133 li r4, (7<<3)
134 li r5, 0x85
135 mr r6, r31
136 bl pci_write_cfg_byte
137
138 /* Set line control */
139 outb UART(LINE_CONTROL), 0x83
140 outb UART(DIVISOR_LATCH_LSB), 0x0c
141 outb UART(DIVISOR_LATCH_MSB), 0x00
142 outb UART(LINE_CONTROL), 0x3
143
144 mtlr r29
145 blr
146
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame^]147
wdenkc7de8292002-11-19 11:04:11 +0000[diff] [blame]148 .globl new_reset
149 .globl new_reset_end
150new_reset:
151 li r0, 0x100
152 oris r0, r0, 0xFFF0
153 mtlr r0
154 blr
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame^]155
156new_reset_end: