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wdenk945af8d2003-07-16 21:53:01 +00001/*
Detlev Zundela21fb982010-01-20 14:28:48 +01002 * (C) Copyright 2000-2010
wdenk945af8d2003-07-16 21:53:01 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <mpc5xxx.h>
Detlev Zundel0f597bc2009-12-18 17:35:57 +010026#include <asm/io.h>
Detlev Zundela21fb982010-01-20 14:28:48 +010027#include <watchdog.h>
wdenk945af8d2003-07-16 21:53:01 +000028
Wolfgang Denkd87080b2006-03-31 18:32:53 +020029DECLARE_GLOBAL_DATA_PTR;
30
wdenk945af8d2003-07-16 21:53:01 +000031/*
32 * Breath some life into the CPU...
33 *
34 * Set up the memory map,
35 * initialize a bunch of registers.
36 */
37void cpu_init_f (void)
38{
Detlev Zundel0f597bc2009-12-18 17:35:57 +010039 volatile struct mpc5xxx_mmap_ctl *mm =
40 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
41 volatile struct mpc5xxx_lpb *lpb =
42 (struct mpc5xxx_lpb *) MPC5XXX_LPB;
Detlev Zundel0f597bc2009-12-18 17:35:57 +010043 volatile struct mpc5xxx_gpio *gpio =
44 (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
45 volatile struct mpc5xxx_xlb *xlb =
46 (struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
Wolfgang Denk9461a932010-01-31 22:03:15 +010047#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
48 volatile struct mpc5xxx_cdm *cdm =
49 (struct mpc5xxx_cdm *) MPC5XXX_CDM;
50#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
Wolfgang Denk13d8bfe2010-01-31 21:58:48 +010051#if defined(CONFIG_WATCHDOG)
Detlev Zundela21fb982010-01-20 14:28:48 +010052 volatile struct mpc5xxx_gpt *gpt0 =
53 (struct mpc5xxx_gpt *) MPC5XXX_GPT;
Wolfgang Denk13d8bfe2010-01-31 21:58:48 +010054#endif /* CONFIG_WATCHDOG */
wdenk945af8d2003-07-16 21:53:01 +000055 unsigned long addecr = (1 << 25); /* Boot_CS */
wdenk945af8d2003-07-16 21:53:01 +000056 /* Pointer is writable since we allocated a register for it */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
wdenk945af8d2003-07-16 21:53:01 +000058
59 /* Clear initial global data */
60 memset ((void *) gd, 0, sizeof (gd_t));
61
62 /*
63 * Memory Controller: configure chip selects and enable them
64 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
Detlev Zundel0f597bc2009-12-18 17:35:57 +010066 out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START));
67 out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START,
68 CONFIG_SYS_BOOTCS_SIZE));
wdenk945af8d2003-07-16 21:53:01 +000069#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#if defined(CONFIG_SYS_BOOTCS_CFG)
Detlev Zundel0f597bc2009-12-18 17:35:57 +010071 out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG);
wdenk945af8d2003-07-16 21:53:01 +000072#endif
73
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
Detlev Zundel0f597bc2009-12-18 17:35:57 +010075 out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START));
76 out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START,
77 CONFIG_SYS_CS0_SIZE));
wdenk945af8d2003-07-16 21:53:01 +000078 /* CS0 and BOOT_CS cannot be enabled at once. */
79 /* addecr |= (1 << 16); */
80#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#if defined(CONFIG_SYS_CS0_CFG)
Detlev Zundel0f597bc2009-12-18 17:35:57 +010082 out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG);
wdenk945af8d2003-07-16 21:53:01 +000083#endif
84
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
Detlev Zundel0f597bc2009-12-18 17:35:57 +010086 out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START));
87 out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START,
88 CONFIG_SYS_CS1_SIZE));
wdenk945af8d2003-07-16 21:53:01 +000089 addecr |= (1 << 17);
90#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#if defined(CONFIG_SYS_CS1_CFG)
Detlev Zundel0f597bc2009-12-18 17:35:57 +010092 out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG);
wdenk945af8d2003-07-16 21:53:01 +000093#endif
94
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
Detlev Zundel0f597bc2009-12-18 17:35:57 +010096 out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START));
97 out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START,
98 CONFIG_SYS_CS2_SIZE));
wdenk945af8d2003-07-16 21:53:01 +000099 addecr |= (1 << 18);
100#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#if defined(CONFIG_SYS_CS2_CFG)
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100102 out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG);
wdenk945af8d2003-07-16 21:53:01 +0000103#endif
104
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100106 out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START));
107 out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START,
108 CONFIG_SYS_CS3_SIZE));
wdenk945af8d2003-07-16 21:53:01 +0000109 addecr |= (1 << 19);
110#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#if defined(CONFIG_SYS_CS3_CFG)
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100112 out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG);
wdenk945af8d2003-07-16 21:53:01 +0000113#endif
114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100116 out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START));
117 out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START,
118 CONFIG_SYS_CS4_SIZE));
wdenk945af8d2003-07-16 21:53:01 +0000119 addecr |= (1 << 20);
120#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#if defined(CONFIG_SYS_CS4_CFG)
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100122 out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG);
wdenk945af8d2003-07-16 21:53:01 +0000123#endif
124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100126 out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START));
127 out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START,
128 CONFIG_SYS_CS5_SIZE));
wdenk945af8d2003-07-16 21:53:01 +0000129 addecr |= (1 << 21);
130#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#if defined(CONFIG_SYS_CS5_CFG)
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100132 out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
wdenk945af8d2003-07-16 21:53:01 +0000133#endif
134
wdenk945af8d2003-07-16 21:53:01 +0000135 addecr |= 1;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100137 out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
138 out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START,
139 CONFIG_SYS_CS6_SIZE));
wdenk945af8d2003-07-16 21:53:01 +0000140 addecr |= (1 << 26);
141#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#if defined(CONFIG_SYS_CS6_CFG)
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100143 out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG);
wdenk945af8d2003-07-16 21:53:01 +0000144#endif
145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100147 out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START));
148 out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START,
149 CONFIG_SYS_CS7_SIZE));
wdenk945af8d2003-07-16 21:53:01 +0000150 addecr |= (1 << 27);
151#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#if defined(CONFIG_SYS_CS7_CFG)
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100153 out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG);
wdenk945af8d2003-07-16 21:53:01 +0000154#endif
155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#if defined(CONFIG_SYS_CS_BURST)
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100157 out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST);
wdenk945af8d2003-07-16 21:53:01 +0000158#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#if defined(CONFIG_SYS_CS_DEADCYCLE)
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100160 out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
wdenk945af8d2003-07-16 21:53:01 +0000161#endif
wdenk945af8d2003-07-16 21:53:01 +0000162
163 /* Enable chip selects */
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100164 out_be32(&mm->ipbi_ws_ctrl, addecr);
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100165 out_be32(&lpb->cs_ctrl, (1 << 24));
wdenk945af8d2003-07-16 21:53:01 +0000166
167 /* Setup pin multiplexing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100169 out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
wdenk945af8d2003-07-16 21:53:01 +0000170#endif
wdenk96dd9af2003-07-31 22:56:30 +0000171
Anatolij Gustschind7903ae2012-08-12 23:38:10 +0000172 /* Setup gpios */
173#if defined(CONFIG_SYS_GPIO_DATADIR)
174 out_be32(&gpio->simple_ddr, CONFIG_SYS_GPIO_DATADIR);
175#endif
176#if defined(CONFIG_SYS_GPIO_OPENDRAIN)
177 out_be32(&gpio->simple_ode, CONFIG_SYS_GPIO_OPENDRAIN);
178#endif
179#if defined(CONFIG_SYS_GPIO_DATAVALUE)
180 out_be32(&gpio->simple_dvo, CONFIG_SYS_GPIO_DATAVALUE);
181#endif
182#if defined(CONFIG_SYS_GPIO_ENABLE)
183 out_be32(&gpio->simple_gpioe, CONFIG_SYS_GPIO_ENABLE);
184#endif
185
wdenk96dd9af2003-07-31 22:56:30 +0000186 /* enable timebase */
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100187 setbits_be32(&xlb->config, (1 << 13));
wdenk7152b1d2003-09-05 23:19:14 +0000188
Wolfgang Denk8419c012006-04-18 11:05:03 +0200189 /* Enable snooping for RAM */
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100190 setbits_be32(&xlb->config, (1 << 15));
191 out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);
Wolfgang Denk8419c012006-04-18 11:05:03 +0200192
Detlev Zundelfd428c02010-03-12 10:01:12 +0100193#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
wdenk7152b1d2003-09-05 23:19:14 +0000194 /* Motorola reports IPB should better run at 133 MHz. */
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100195 setbits_be32(&mm->ipbi_ws_ctrl, 1);
wdenk7152b1d2003-09-05 23:19:14 +0000196 /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100197 addecr = in_be32(&cdm->cfg);
wdenk7152b1d2003-09-05 23:19:14 +0000198 addecr &= ~0x103;
Detlev Zundelfd428c02010-03-12 10:01:12 +0100199# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
wdenk56523f12004-07-11 17:40:54 +0000200 /* pci_clk_sel = 0x01 -> IPB_CLK/2 */
201 addecr |= 0x01;
Detlev Zundelfd428c02010-03-12 10:01:12 +0100202# else
wdenk56523f12004-07-11 17:40:54 +0000203 /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
wdenk7152b1d2003-09-05 23:19:14 +0000204 addecr |= 0x02;
Detlev Zundelfd428c02010-03-12 10:01:12 +0100205# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100206 out_be32(&cdm->cfg, addecr);
Detlev Zundelfd428c02010-03-12 10:01:12 +0100207#endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
wdenk4aeb2512003-09-16 17:06:05 +0000208 /* Configure the XLB Arbiter */
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100209 out_be32(&xlb->master_pri_enable, 0xff);
210 out_be32(&xlb->master_priority, 0x11111111);
wdenke1599e82004-10-10 23:27:33 +0000211
Detlev Zundelfd428c02010-03-12 10:01:12 +0100212#if defined(CONFIG_SYS_XLB_PIPELINING)
wdenke1599e82004-10-10 23:27:33 +0000213 /* Enable piplining */
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100214 clrbits_be32(&xlb->config, (1 << 31));
Detlev Zundelfd428c02010-03-12 10:01:12 +0100215#endif
Detlev Zundela21fb982010-01-20 14:28:48 +0100216
217#if defined(CONFIG_WATCHDOG)
218 /* Charge the watchdog timer - prescaler = 64k, count = 64k*/
219 out_be32(&gpt0->cir, 0x0000ffff);
220 out_be32(&gpt0->emsr, 0x9004); /* wden|ce|timer_ms */
221
222 reset_5xxx_watchdog();
223#endif /* CONFIG_WATCHDOG */
wdenk945af8d2003-07-16 21:53:01 +0000224}
225
226/*
227 * initialize higher level parts of CPU like time base and timers
228 */
229int cpu_init_r (void)
230{
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100231 volatile struct mpc5xxx_intr *intr =
232 (struct mpc5xxx_intr *) MPC5XXX_ICTL;
233
wdenk945af8d2003-07-16 21:53:01 +0000234 /* mask all interrupts */
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100235 out_be32(&intr->per_mask, 0xffffff00);
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100236 setbits_be32(&intr->main_mask, 0x0001ffff);
237 clrbits_be32(&intr->ctrl, 0x00000f00);
wdenk4aeb2512003-09-16 17:06:05 +0000238 /* route critical ints to normal ints */
Detlev Zundel0f597bc2009-12-18 17:35:57 +0100239 setbits_be32(&intr->ctrl, 0x00000001);
wdenk945af8d2003-07-16 21:53:01 +0000240
Jon Loeliger44312832007-07-09 19:06:00 -0500241#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
wdenk945af8d2003-07-16 21:53:01 +0000242 /* load FEC microcode */
243 loadtask(0, 2);
244#endif
245
246 return (0);
247}