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gerrit.cesnet.cz / github / trini / u-boot / 8bba6cc0db3f72b313c0e45ae57d9b733ab00249 / . / board / nvidia / jetson-tk1 / pinmux-config-jetson-tk1.h
blob: 863721b2a33084947d515cb19ddb8369f7259e9e [file] [log] [blame]
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]1/*
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _PINMUX_CONFIG_JETSON_TK1_H_
8#define _PINMUX_CONFIG_JETSON_TK1_H_
9
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]10#define GPIO_INIT(_gpio, _init) \
11 { \
12 .gpio = GPIO_P##_gpio, \
13 .init = TEGRA_GPIO_INIT_##_init, \
14 }
15
16static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
17 /* gpio, init_val */
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]18 GPIO_INIT(G0, IN),
19 GPIO_INIT(G1, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]20 GPIO_INIT(G2, IN),
21 GPIO_INIT(G3, IN),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]22 GPIO_INIT(G4, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]23 GPIO_INIT(H2, OUT0),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]24 GPIO_INIT(H4, IN),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]25 GPIO_INIT(H7, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]26 GPIO_INIT(I0, OUT0),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]27 GPIO_INIT(I1, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]28 GPIO_INIT(I6, IN),
29 GPIO_INIT(J0, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]30 GPIO_INIT(K1, OUT0),
31 GPIO_INIT(K2, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]32 GPIO_INIT(K4, OUT0),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]33 GPIO_INIT(K6, OUT0),
34 GPIO_INIT(N7, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]35 GPIO_INIT(O1, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]36 GPIO_INIT(O4, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]37 GPIO_INIT(P2, OUT0),
38 GPIO_INIT(Q0, IN),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]39 GPIO_INIT(Q3, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]40 GPIO_INIT(Q5, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]41 GPIO_INIT(R0, OUT0),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]42 GPIO_INIT(R2, OUT0),
43 GPIO_INIT(R4, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]44 GPIO_INIT(R7, IN),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]45 GPIO_INIT(S7, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]46 GPIO_INIT(T0, OUT0),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]47 GPIO_INIT(T1, IN),
48 GPIO_INIT(U0, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]49 GPIO_INIT(U1, IN),
50 GPIO_INIT(U2, IN),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]51 GPIO_INIT(U3, IN),
52 GPIO_INIT(U4, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]53 GPIO_INIT(U5, IN),
54 GPIO_INIT(U6, IN),
55 GPIO_INIT(V0, IN),
56 GPIO_INIT(V1, IN),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]57 GPIO_INIT(X1, IN),
58 GPIO_INIT(X4, IN),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]59 GPIO_INIT(X7, OUT0),
60 GPIO_INIT(BB3, OUT0),
61 GPIO_INIT(BB5, OUT0),
62 GPIO_INIT(BB6, OUT0),
63 GPIO_INIT(BB7, OUT0),
64 GPIO_INIT(CC1, IN),
65 GPIO_INIT(CC2, IN),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]66 GPIO_INIT(EE2, OUT1),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]67};
68
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]69#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
70 { \
71 .pingrp = PMUX_PINGRP_##_pingrp, \
72 .func = PMUX_FUNC_##_mux, \
73 .pull = PMUX_PULL_##_pull, \
74 .tristate = PMUX_TRI_##_tri, \
75 .io = PMUX_PIN_##_io, \
76 .od = PMUX_PIN_OD_##_od, \
77 .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
78 .lock = PMUX_PIN_LOCK_DEFAULT, \
79 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
80 }
81
82static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
83 /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]84 PINCFG(CLK_32K_OUT_PA0, SOC, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
85 PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
86 PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
87 PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
88 PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
89 PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
90 PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]91 PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]92 PINCFG(PB0, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
93 PINCFG(PB1, UARTD, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]94 PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
95 PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
96 PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
97 PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]98 PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]99 PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]100 PINCFG(UART2_RXD_PC3, IRDA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]101 PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
102 PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]103 PINCFG(PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
104 PINCFG(PG0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
105 PINCFG(PG1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
106 PINCFG(PG2, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
107 PINCFG(PG3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
108 PINCFG(PG4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]109 PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
110 PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]111 PINCFG(PG7, SPI4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]112 PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
113 PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]114 PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]115 PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
116 PINCFG(PH4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
117 PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
118 PINCFG(PH6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
119 PINCFG(PH7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]120 PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]121 PINCFG(PI1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
122 PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]123 PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]124 PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
125 PINCFG(PI5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
126 PINCFG(PI6, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]127 PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]128 PINCFG(PJ0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
129 PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
130 PINCFG(UART2_CTS_N_PJ5, UARTB, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]131 PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
132 PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]133 PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]134 PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]135 PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
136 PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]137 PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]138 PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]139 PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]140 PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]141 PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
142 PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]143 PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]144 PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
145 PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
146 PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
147 PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, TRISTATE, INPUT, DEFAULT, NORMAL),
148 PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
149 PINCFG(ULPI_DATA0_PO1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
150 PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
151 PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
152 PINCFG(ULPI_DATA3_PO4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
153 PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
154 PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
155 PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
156 PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
157 PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]158 PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]159 PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]160 PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
161 PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
162 PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
163 PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
164 PINCFG(KB_COL0_PQ0, DEFAULT, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
165 PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
166 PINCFG(KB_COL2_PQ2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
167 PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
168 PINCFG(KB_COL4_PQ4, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
169 PINCFG(KB_COL5_PQ5, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
170 PINCFG(KB_COL6_PQ6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
171 PINCFG(KB_COL7_PQ7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]172 PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]173 PINCFG(KB_ROW1_PR1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]174 PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]175 PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
176 PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
177 PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
178 PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
179 PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
180 PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
181 PINCFG(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
182 PINCFG(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
183 PINCFG(KB_ROW11_PS3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
184 PINCFG(KB_ROW12_PS4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
185 PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
186 PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
187 PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]188 PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]189 PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]190 PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
191 PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
192 PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]193 PINCFG(PU0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
194 PINCFG(PU1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
195 PINCFG(PU2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
196 PINCFG(PU3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
197 PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
198 PINCFG(PU5, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
199 PINCFG(PU6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
200 PINCFG(PV0, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
201 PINCFG(PV1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
202 PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]203 PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
204 PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
205 PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]206 PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
207 PINCFG(GPIO_W3_AUD_PW3, SPI6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]208 PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
209 PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]210 PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
211 PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]212 PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]213 PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]214 PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]215 PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
216 PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
217 PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
218 PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]219 PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]220 PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]221 PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]222 PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
223 PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]224 PINCFG(SDMMC1_DAT3_PY4, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
225 PINCFG(SDMMC1_DAT2_PY5, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
226 PINCFG(SDMMC1_DAT1_PY6, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
227 PINCFG(SDMMC1_DAT0_PY7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
228 PINCFG(SDMMC1_CLK_PZ0, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
229 PINCFG(SDMMC1_CMD_PZ1, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]230 PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
231 PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
232 PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
233 PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
234 PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
235 PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
236 PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
237 PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
238 PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
239 PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
240 PINCFG(PBB0, VIMCLK2_ALT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
241 PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
242 PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]243 PINCFG(PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]244 PINCFG(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren93485322014-04-22 14:37:55 -0600[diff] [blame]245 PINCFG(PBB5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
246 PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
247 PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]248 PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]249 PINCFG(PCC1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
250 PINCFG(PCC2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]251 PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]252 PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
Stephen Warren606f5bc2014-08-22 15:04:08 -0600[diff] [blame]253 PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]254 PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
255 PINCFG(PEX_WAKE_N_PDD3, PE, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warren606f5bc2014-08-22 15:04:08 -0600[diff] [blame]256 PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]257 PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]258 PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]259 PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
260 PINCFG(DAP_MCLK1_REQ_PEE2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
261 PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]262 PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
263 PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]264 PINCFG(DP_HPD_PFF0, DP, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
265 PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
266 PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]267 PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]268 PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
269 PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
270 PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]271 PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
Stephen Warrenc1fe92f2015-02-18 13:27:04 -0700[diff] [blame]272 PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
Stephen Warrene04bfda2014-03-25 11:39:33 -0600[diff] [blame]273 PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
274};
275
276#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
277 { \
278 .drvgrp = PMUX_DRVGRP_##_drvgrp, \
279 .slwf = _slwf, \
280 .slwr = _slwr, \
281 .drvup = _drvup, \
282 .drvdn = _drvdn, \
283 .lpmd = PMUX_LPMD_##_lpmd, \
284 .schmt = PMUX_SCHMT_##_schmt, \
285 .hsm = PMUX_HSM_##_hsm, \
286 }
287
288static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = {
289};
290
291#endif /* PINMUX_CONFIG_JETSON_TK1_H */