blob: af0853b0d7e9fd5f65377992dce354369cbb0a36 [file] [log] [blame]
Kumar Gala47d41cc2009-02-05 20:40:57 -06001/*
2 * Copyright 2009 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_CONFIG_H_
22#define _ASM_CONFIG_H_
23
Kumar Gala87c90632009-02-05 20:40:58 -060024#ifndef CONFIG_MAX_MEM_MAPPED
Becky Brucebd767292009-02-23 13:56:51 -060025#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
Kumar Gala87c90632009-02-05 20:40:58 -060026#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
27#else
Stefan Roese2ede8792009-02-11 09:37:12 +010028#define CONFIG_MAX_MEM_MAPPED (256 << 20)
Kumar Gala87c90632009-02-05 20:40:58 -060029#endif
30#endif
31
Peter Tyserf732a752009-07-15 00:01:08 -050032/* Check if boards need to enable FSL DMA engine for SDRAM init */
33#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
34#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
35 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
36 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
Peter Tyser017f11f2009-06-30 17:15:40 -050037#define CONFIG_FSL_DMA
Kumar Gala47d41cc2009-02-05 20:40:57 -060038#endif
Peter Tyser017f11f2009-06-30 17:15:40 -050039#endif
40
Poonam Aggrwal3b1f2432009-08-20 18:55:35 +053041#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
42 defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
Kumar Gala7e4259b2009-03-19 02:39:17 -050043#define CONFIG_MAX_CPUS 2
44#elif defined(CONFIG_PPC_P4080)
45#define CONFIG_MAX_CPUS 8
Poonam Aggrwal0e870982009-07-31 12:08:14 +053046#else
Kumar Gala7e4259b2009-03-19 02:39:17 -050047#define CONFIG_MAX_CPUS 1
Poonam Aggrwal0e870982009-07-31 12:08:14 +053048#endif
49
Peter Tyser5ccd29c2009-10-23 15:55:47 -050050/*
51 * Provide a default boot page translation virtual address that lines up with
52 * Freescale's default e500 reset page.
53 */
54#if (defined(CONFIG_E500) && defined(CONFIG_MP))
55#ifndef CONFIG_BPTR_VIRT_ADDR
56#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
57#endif
58#endif
59
Peter Tyser85829012009-09-21 11:20:25 -050060/* Relocation to SDRAM works on all PPC boards */
61#define CONFIG_RELOC_FIXUP_WORKS
62
Peter Tyser017f11f2009-06-30 17:15:40 -050063#endif /* _ASM_CONFIG_H_ */