| Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 1 | CONFIG_X86=y |
| Bin Meng | 65c4ac0 | 2015-04-27 23:22:24 +0800 | [diff] [blame] | 2 | CONFIG_VENDOR_INTEL=y |
| Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 3 | CONFIG_DEFAULT_DEVICE_TREE="minnowmax" |
| Joe Hershberger | bd328eb | 2015-05-12 14:46:24 -0500 | [diff] [blame] | 4 | CONFIG_TARGET_MINNOWMAX=y |
| 5 | CONFIG_HAVE_INTEL_ME=y |
| Simon Glass | 281239a | 2015-04-29 22:26:03 -0600 | [diff] [blame] | 6 | CONFIG_SMP=y |
| Bin Meng | aeda4ab | 2015-07-09 18:37:40 +0800 | [diff] [blame] | 7 | CONFIG_HAVE_VGA_BIOS=y |
| Joe Hershberger | bd328eb | 2015-05-12 14:46:24 -0500 | [diff] [blame] | 8 | CONFIG_GENERATE_SFI_TABLE=y |
| 9 | CONFIG_CMD_CPU=y |
| Joe Hershberger | ef0f2f5 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 10 | # CONFIG_CMD_IMLS is not set |
| 11 | # CONFIG_CMD_FLASH is not set |
| 12 | # CONFIG_CMD_SETEXPR is not set |
| 13 | # CONFIG_CMD_NFS is not set |
| Joe Hershberger | c9bb942 | 2015-06-22 16:15:29 -0500 | [diff] [blame] | 14 | CONFIG_BOOTSTAGE=y |
| 15 | CONFIG_BOOTSTAGE_REPORT=y |
| 16 | CONFIG_CMD_BOOTSTAGE=y |
| Joe Hershberger | bd328eb | 2015-05-12 14:46:24 -0500 | [diff] [blame] | 17 | CONFIG_OF_CONTROL=y |
| 18 | CONFIG_CPU=y |
| Bin Meng | aeda4ab | 2015-07-09 18:37:40 +0800 | [diff] [blame] | 19 | CONFIG_DM_PCI=y |
| Joe Hershberger | c9bb942 | 2015-06-22 16:15:29 -0500 | [diff] [blame] | 20 | CONFIG_SPI_FLASH=y |
| 21 | CONFIG_VIDEO_VESA=y |
| 22 | CONFIG_FRAMEBUFFER_SET_VESA_MODE=y |
| 23 | CONFIG_FRAMEBUFFER_VESA_MODE_11A=y |
| Bin Meng | 93f8a31 | 2015-07-15 16:23:39 +0800 | [diff] [blame] | 24 | CONFIG_DM_RTC=y |
| Joe Hershberger | c9bb942 | 2015-06-22 16:15:29 -0500 | [diff] [blame] | 25 | CONFIG_USE_PRIVATE_LIBGCC=y |
| 26 | CONFIG_SYS_VSNPRINTF=y |
| Simon Glass | bbbe55f | 2015-08-02 18:07:21 -0600 | [diff] [blame] | 27 | CONFIG_DEBUG_UART=y |
| 28 | CONFIG_DEBUG_UART_NS16550=y |
| 29 | CONFIG_DEBUG_UART_BASE=0x3f8 |
| 30 | CONFIG_DEBUG_UART_CLOCK=1843200 |